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Wed, 5 Dec 2018 06:32:50 +0000 (GMT) Received: from eucas1p2.samsung.com ( [182.198.249.207]) by eusmges2new.samsung.com (EUCPMTA) with SMTP id AE.41.04294.211770C5; Wed, 5 Dec 2018 06:32:50 +0000 (GMT) Received: from eusmgms1.samsung.com (unknown [182.198.249.179]) by eucas1p1.samsung.com (KnoxPortal) with ESMTP id 20181205063250eucas1p1819de50c3030fb60a704656be878fff2~tXCcNpj0x1627616276eucas1p1N; Wed, 5 Dec 2018 06:32:50 +0000 (GMT) X-AuditID: cbfec7f4-835ff700000010c6-8e-5c077112c2f5 Received: from eusync3.samsung.com ( [203.254.199.213]) by eusmgms1.samsung.com (EUCPMTA) with SMTP id F0.C7.04284.111770C5; Wed, 5 Dec 2018 06:32:50 +0000 (GMT) Received: from localhost.localdomain ([10.88.100.192]) by eusync3.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0PJ900CCM3I7V060@eusync3.samsung.com>; Wed, 05 Dec 2018 06:32:49 +0000 (GMT) From: Jungseung Lee To: Marek Vasut , David Woodhouse , Brian Norris , Boris Brezillon , Richard Weinberger , linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, js07.lee@samsung.com, js07.lee@gmail.com Subject: [RFC PATCH 2/2] mtd: spi-nor: support lock/unlock for a few Micron chips Date: Wed, 05 Dec 2018 15:32:20 +0900 Message-id: <20181205063220.22279-2-js07.lee@samsung.com> X-Mailer: git-send-email 2.17.1 In-reply-to: <20181205063220.22279-1-js07.lee@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrHIsWRmVeSWpSXmKPExsWy7djP87pChewxBm3X5Cz2nepnsThyYS2z xcSVk5kt/s55x2Tx6OZvVovLu+awWexuWsZucXTPPWaLyTvfMDpwesxbU+2xc9Zddo/NK7Q8 Ni+p97g5r9Cjb8sqRo/Pm+QC2KO4bFJSczLLUov07RK4Mt78msNesJavor13BlMD4x3uLkZO DgkBE4nvhzqZuxi5OIQEVjBKvJt5hBXC+cwoceD4WhaYqp3bHzFBJJYxStzY3cIO4fxjlFgz o5MRpIpNQEvixu9NYO0iAnuZJP6dOMAOkhAWCJZoaV3OBmKzCKhKzHuziwnE5hWwlDjf9gZq hbzE6g0HmEFsTgEriTVt/YwggyQEJrBJ7Di5BWgqB5DjIrHyQDREvbDEq+Nb2CFsGYnOjoNM EHaxxM6VE9khelsYJR4tXwJVZCzx7u1asAXMAnwSk7ZNZ4aYySvR0SYEUeIhcfrsLmhg9DJK fNz3hH0Co8QCRoZVjOKppcW56anFRnmp5XrFibnFpXnpesn5uZsYgbF4+t/xLzsYd/1JOsQo wMGoxMMrMYUtRog1say4MvcQowQHs5II7wob9hgh3pTEyqrUovz4otKc1OJDjNIcLErivNUM D6KFBNITS1KzU1MLUotgskwcnFINjA7TFn2eM182NDapY3Ng3U+H+JnV3UULFNzP3Dwx955E b+JipXkrWu+0T/wX9vPrB8X1PbfSbYw0nrlU1M968mnm/X9FDVF/JqQxnpezLnR7E7c/87Su otVkXtnKljWL++fPneGv+Lr08ye2m/90GueqZOYUCk7knPxh1mSHoBcXnRX4JhrcWqTEUpyR aKjFXFScCADpRIrWwQIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupiluLIzCtJLcpLzFFi42I5/e/4VV2hQvYYg/4Ai32n+lksjlxYy2wx ceVkZou/c94xWTy6+ZvV4vKuOWwWu5uWsVsc3XOP2WLyzjeMDpwe89ZUe+ycdZfdY/MKLY/N S+o9bs4r9OjbsorR4/MmuQD2KC6blNSczLLUIn27BK6MN7/msBes5ato753B1MB4h7uLkZND QsBEYuf2R0wgtpDAEkaJ5tv1XYxcQHYDk8TF3ifsIAk2AS2JG783sYIkRAT2MkkcPTWbDSQh LBAs0dK6HMxmEVCVmPdmF9gkXgFLifNtb1ggNshLrN5wgBnE5hSwkljT1s8Isc1S4tfmZawT GLkXMDKsYhRJLS3OTc8tNtQrTswtLs1L10vOz93ECAyhbcd+bt7BeGlj8CFGAQ5GJR5eySls MUKsiWXFlbmHGCU4mJVEeFfYsMcI8aYkVlalFuXHF5XmpBYfYpTmYFES5z1vUBklJJCeWJKa nZpakFoEk2Xi4JRqYNQU7M74tfXH48CJfDcPp2jXP3l01GP+/hnZIVHqplMmirD/qvT8FftR k6l18s0W8eDJlxbPlM883/5GxGCpzaq52lGu9cxnNB4Ynn2afXleMZfx2oKuf7VP86ZI/K9K 5GvxX9aUvmnnm0ML+crl+eaZP9/aK7w0udj4C7tGzqFPRwWnMuX8yVJiKc5INNRiLipOBACV 4GrTHQIAAA== X-CMS-MailID: 20181205063250eucas1p1819de50c3030fb60a704656be878fff2 X-Msg-Generator: CA CMS-TYPE: 201P X-CMS-RootMailID: 20181205063250eucas1p1819de50c3030fb60a704656be878fff2 References: <20181205063220.22279-1-js07.lee@samsung.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Some Micron models are known to have lock/unlock support, and that also support 4bit block protection bit (bp0-3). This patch support lock/unlock feature on the flash. Tested on w25q512ax3. The Other is modified following the datasheet. Signed-off-by: Jungseung Lee --- drivers/mtd/spi-nor/spi-nor.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index c261d8f7bef4..25d2abb842c0 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -1438,8 +1438,16 @@ static const struct flash_info spi_nor_ids[] = { { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) }, { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { "n25q256ax1", INFO(0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) }, - { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, - { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, + { + "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, + SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_HAS_BP3) + }, + { + "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, + SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_HAS_BP3) + }, { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, { "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, { "mt25qu02g", INFO(0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, -- 2.17.1