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received-spf: None (protection.outlook.com: cavium.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: pHHYG4I9bIL0W4wBYDrt7mg1LnOYZRN0euiSl+rRsI6oVz4H+usvRRB3xPOKTND8o3NBXOBSxEc4tx0MFjcKtfKyLtNmQX5l8cfwZv1eRXmGa/r2c9E2Z6guT5fhF0vCpPhOVnwYy33acbZwBg386N6raKLKsszCE2ssUt8Sax6tPnn8jWmUX/oskk6ORj5GOvrvzx/vyZypFbduT8L15/oZmDDLJ7MmLopB93/JcnhsBhjDR4wqTPfI2u2mGbE6Fb9nLc/bgD2RMAE5HKn2sixrl1AmE62s20GpYmFr0fbamIH3BkNJT9ObMLnnZ64Lz4tVPbFskMdcLCof91UXt41m0brdd0EUiFCw94T7Ac0= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: cavium.com X-MS-Exchange-CrossTenant-Network-Message-Id: 1efc9710-a569-452e-d6eb-08d65aa0ba25 X-MS-Exchange-CrossTenant-originalarrivaltime: 05 Dec 2018 10:59:28.7335 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 711e4ccf-2e9b-4bcf-a551-4094005b6194 X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR07MB4821 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The SoC has PMU support in its L3 cache controller (L3C) and in the DDR4 Memory Controller (DMC). Signed-off-by: Ganapatrao Kulkarni --- Documentation/perf/thunderx2-pmu.txt | 93 ++++++++++++++++++++++++++++ 1 file changed, 93 insertions(+) create mode 100644 Documentation/perf/thunderx2-pmu.txt diff --git a/Documentation/perf/thunderx2-pmu.txt b/Documentation/perf/thun= derx2-pmu.txt new file mode 100644 index 000000000000..f8835bf1068c --- /dev/null +++ b/Documentation/perf/thunderx2-pmu.txt @@ -0,0 +1,93 @@ + +Cavium ThunderX2 SoC Performance Monitoring Unit (PMU UNCORE) +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +ThunderX2 SoC PMU consists of independent system wide per Socket PMUs, suc= h +as Level 3 Cache(L3C) and DDR4 Memory Controller(DMC). + +The DMC has 8 interleaved channels and the L3C has 16 interleaved tiles. E= vents +are counted for default channel(i.e channel 0) and prorated to total numbe= r of +channels/tiles. + +DMC and L3C supports up to 4 counters. Counters are independently programm= able +and can be started and stopped individually. Each counter can be set to +different event. Counters are 32 bit and do not support overflow interrupt= ; +they are read every 2 seconds. + +PMU UNCORE (perf) driver: + +The thunderx2_pmu driver registers per socket perf PMUs for DMC and L3C de= vices. +Each PMU can be used to count up to 4 events simultaneously. PMUs provide +description of its available events and configuration options +in sysfs, see /sys/devices/uncore_; S is the socket id. + +The driver does not support sampling, therefore "perf record" will +not work. Per-task perf sessions are not supported. + +Examples: + +perf stat -a -e uncore_dmc_0/cnt_cycles/ sleep 1 + +perf stat -a -e \ +uncore_dmc_0/cnt_cycles/,\ +uncore_dmc_0/data_transfers/,\ +uncore_dmc_0/read_txns/,\ +uncore_dmc_0/write_txns/ sleep 1 + +perf stat -a -e \ +uncore_l3c_0/read_request/,\ +uncore_l3c_0/read_hit/,\ +uncore_l3c_0/inv_request/,\ +uncore_l3c_0/inv_hit/ sleep 1 + + +L3C events: +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +read_request: + Number of Read requests received by the L3 Cache. + This include Read as well as Read Exclusives. + +read_hit: + Number of Read requests received by the L3 cache that were hit + in the L3 (Data provided form the L3) + +writeback_request: + Number of Write Backs received by the L3 Cache. These are basically + the L2 Evicts and writes from the PCIe Write Cache. + +inv_nwrite_request: + This is the Number of Invalidate and Write received by the L3 Cache. + Also Writes from IO that did not go through the PCIe Write Cache. + +inv_nwrite_hit + This is the Number of Invalidate and Write received by the L3 Cache + That were a hit in the L3 Cache. + +inv_request: + Number of Invalidate request received by the L3 Cache. + +inv_hit: + Number of Invalidate request received by the L3 Cache that were a + hit in L3. + +evict_request: + Number of Evicts that the L3 generated. + +NOTE: +1. Granularity of all these events counter value is cache line length(64 B= ytes). +2. L3C cache Hit Ratio =3D (read_hit + inv_nwrite_hit + inv_hit) / (read_r= equest + inv_nwrite_request + inv_request) + +DMC events: +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +cnt_cycles: + Count cycles (Clocks at the DMC clock rate) + +write_txns: + Number of 64 Bytes write transactions received by the DMC(s) + +read_txns: + Number of 64 Bytes Read transactions received by the DMC(s) + +data_transfers: + Number of 64 Bytes data transferred to or from DRAM. --=20 2.18.0