From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A313EC43387 for ; Wed, 26 Dec 2018 08:13:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7EABB21720 for ; Wed, 26 Dec 2018 08:13:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726604AbeLZIMv (ORCPT ); Wed, 26 Dec 2018 03:12:51 -0500 Received: from mga11.intel.com ([192.55.52.93]:64132 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726432AbeLZIMr (ORCPT ); Wed, 26 Dec 2018 03:12:47 -0500 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 26 Dec 2018 00:12:46 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.56,400,1539673200"; d="scan'208";a="104759687" Received: from unknown (HELO localhost.localdomain.sh.intel.com) ([10.239.13.104]) by orsmga008.jf.intel.com with ESMTP; 26 Dec 2018 00:12:45 -0800 From: Yang Weijiang To: pbonzini@redhat.com, rkrcmar@redhat.com, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, mst@redhat.com, yu-cheng.yu@intel.com, yi.z.zhang@intel.com, hjl.tools@gmail.com Cc: Yang Weijiang , Zhang Yi Z Subject: [PATCH v1 5/8] kvm:x86 Enable MSR_IA32_XSS bit 11 and 12 for CET xsaves/xrstors. Date: Wed, 26 Dec 2018 16:15:29 +0800 Message-Id: <20181226081532.30698-6-weijiang.yang@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181226081532.30698-1-weijiang.yang@intel.com> References: <20181226081532.30698-1-weijiang.yang@intel.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org For kvm Guest OS, right now, only bit 11(user mode CET) and bit 12 (supervisor CET) are supported in XSS MSR, if other bits are being set, the write to XSS will be skipped. Signed-off-by: Zhang Yi Z Signed-off-by: Yang Weijiang --- arch/x86/kvm/vmx.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c index fa2db6248404..5739ab393b90 100644 --- a/arch/x86/kvm/vmx.c +++ b/arch/x86/kvm/vmx.c @@ -47,6 +47,7 @@ #include #include #include +#include #include #include #include @@ -4323,12 +4324,16 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) case MSR_IA32_XSS: if (!vmx_xsaves_supported()) return 1; + /* - * The only supported bit as of Skylake is bit 8, but - * it is not supported on KVM. + * Right now, only support XSS_CET_U[bit 11] and + * XSS_CET_S[bit 12] in MSR_IA32_XSS. */ - if (data != 0) + + if (data & ~(XFEATURE_MASK_SHSTK_USER + | XFEATURE_MASK_SHSTK_KERNEL)) return 1; + vcpu->arch.ia32_xss = data; if (vcpu->arch.ia32_xss != host_xss) add_atomic_switch_msr(vmx, MSR_IA32_XSS, -- 2.17.1