From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.5 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,INCLUDES_PATCH,MAILING_LIST_MULTI, MENTIONS_GIT_HOSTING,SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AFD67C43387 for ; Fri, 4 Jan 2019 18:34:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7FFD4218F0 for ; Fri, 4 Jan 2019 18:34:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1546626878; bh=3mId3pt9Jm5uJl1VIqC/DGhPe/narMsvoKXRYbBQ6Bw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=ePWeoVLhf37HDqazR6bie/WFEOQhxXi+L8rElQg31vo0q5HHly+s6wjO2iNwnZeY3 zNym90gn0NH1FrXyl/he6Y/0A6tMNB9h7s3TvP/Fo7NotRyT9v7En3E9wu0241z50p 1XPuPcG5mDcWVAzEwU2YmAimfRXQNuznr2XX+ykw= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728723AbfADSeh (ORCPT ); Fri, 4 Jan 2019 13:34:37 -0500 Received: from mail.kernel.org ([198.145.29.99]:53328 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728632AbfADSed (ORCPT ); Fri, 4 Jan 2019 13:34:33 -0500 Received: from quaco.ghostprotocols.net (unknown [179.97.41.186]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 44203218E0; Fri, 4 Jan 2019 18:34:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1546626872; bh=3mId3pt9Jm5uJl1VIqC/DGhPe/narMsvoKXRYbBQ6Bw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=BiMdyXOt38jnEyP5QJdp1HxnwGnqRNFGWNdNkJwip0uEPQiehlEgcwuB1V26kqCrR 9iJtxCwm6IEvQHK5qJr2hiQyPUsA85smfssE+ySdctU+cMo+SBUnCk0nNh0mEfdR1r Jlzv5giJdm/Yr0A5G/6Ok2rxITM1yCPgtxYMkeC8= From: Arnaldo Carvalho de Melo To: Ingo Molnar Cc: Clark Williams , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Arnaldo Carvalho de Melo , Adrian Hunter , Jiri Olsa , Namhyung Kim , Paolo Bonzini , Robert Hoo , Thomas Gleixner , Thomas Lendacky Subject: [PATCH 11/16] tools headers x86: Sync asm/cpufeatures.h copy with the kernel sources Date: Fri, 4 Jan 2019 15:33:32 -0300 Message-Id: <20190104183337.12771-12-acme@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190104183337.12771-1-acme@kernel.org> References: <20190104183337.12771-1-acme@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Arnaldo Carvalho de Melo To get the changes from: a0aea130afeb ("KVM: x86: Add CPUID support for new instruction WBNOINVD") 20c3a2c33e9f ("x86/speculation: Add support for STIBP always-on preferred mode") Cc: Adrian Hunter Cc: Jiri Olsa Cc: Namhyung Kim Cc: Paolo Bonzini Cc: Robert Hoo Cc: Thomas Gleixner Cc: Thomas Lendacky Link: https://lkml.kernel.org/n/tip-aonti3bu9rhnqe5hlawbidcp@git.kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/arch/x86/include/asm/cpufeatures.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tools/arch/x86/include/asm/cpufeatures.h b/tools/arch/x86/include/asm/cpufeatures.h index 28c4a502b419..6d6122524711 100644 --- a/tools/arch/x86/include/asm/cpufeatures.h +++ b/tools/arch/x86/include/asm/cpufeatures.h @@ -281,9 +281,11 @@ #define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */ #define X86_FEATURE_IRPERF (13*32+ 1) /* Instructions Retired Count */ #define X86_FEATURE_XSAVEERPTR (13*32+ 2) /* Always save/restore FP error pointers */ +#define X86_FEATURE_WBNOINVD (13*32+ 9) /* WBNOINVD instruction */ #define X86_FEATURE_AMD_IBPB (13*32+12) /* "" Indirect Branch Prediction Barrier */ #define X86_FEATURE_AMD_IBRS (13*32+14) /* "" Indirect Branch Restricted Speculation */ #define X86_FEATURE_AMD_STIBP (13*32+15) /* "" Single Thread Indirect Branch Predictors */ +#define X86_FEATURE_AMD_STIBP_ALWAYS_ON (13*32+17) /* "" Single Thread Indirect Branch Predictors always-on preferred */ #define X86_FEATURE_AMD_SSBD (13*32+24) /* "" Speculative Store Bypass Disable */ #define X86_FEATURE_VIRT_SSBD (13*32+25) /* Virtualized Speculative Store Bypass Disable */ #define X86_FEATURE_AMD_SSB_NO (13*32+26) /* "" Speculative Store Bypass is fixed in hardware. */ -- 2.20.1