From: Yang Weijiang <weijiang.yang@intel.com>
To: Jim Mattson <jmattson@google.com>
Cc: "Sean Christopherson" <sean.j.christopherson@intel.com>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Radim Krčmář" <rkrcmar@redhat.com>,
LKML <linux-kernel@vger.kernel.org>,
"kvm list" <kvm@vger.kernel.org>,
"Michael S. Tsirkin" <mst@redhat.com>,
yu-cheng.yu@intel.com, yi.z.zhang@intel.com, hjl.tools@gmail.com,
"Zhang Yi Z" <yi.z.zhang@linux.intel.com>
Subject: Re: [PATCH v1 5/8] kvm:x86 Enable MSR_IA32_XSS bit 11 and 12 for CET xsaves/xrstors.
Date: Mon, 7 Jan 2019 05:17:59 +0800 [thread overview]
Message-ID: <20190106211759.GA19372@local-michael-cet-test.sh.intel.com> (raw)
In-Reply-To: <CALMp9eS3F5siy-VhKwEiP+J3m3AeQ3WjvEkVPvvWZ-WMrqQYsw@mail.gmail.com>
On Wed, Jan 02, 2019 at 11:19:34AM -0800, Jim Mattson wrote:
Thanks Sean and Jim for your valuable comments, I'll consolidate them in
next release!
> On Wed, Jan 2, 2019 at 10:24 AM Sean Christopherson
> <sean.j.christopherson@intel.com> wrote:
> >
> > On Wed, Dec 26, 2018 at 04:15:29PM +0800, Yang Weijiang wrote:
> > > For kvm Guest OS, right now, only bit 11(user mode CET) and bit 12
> > > (supervisor CET) are supported in XSS MSR, if other bits are being set,
> > > the write to XSS will be skipped.
> > >
> > > Signed-off-by: Zhang Yi Z <yi.z.zhang@linux.intel.com>
> > > Signed-off-by: Yang Weijiang <weijiang.yang@intel.com>
> > > ---
> > > arch/x86/kvm/vmx.c | 11 ++++++++---
> > > 1 file changed, 8 insertions(+), 3 deletions(-)
> > >
> > > diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
> > > index fa2db6248404..5739ab393b90 100644
> > > --- a/arch/x86/kvm/vmx.c
> > > +++ b/arch/x86/kvm/vmx.c
> > > @@ -47,6 +47,7 @@
> > > #include <asm/virtext.h>
> > > #include <asm/mce.h>
> > > #include <asm/fpu/internal.h>
> > > +#include <asm/fpu/types.h>
> > > #include <asm/perf_event.h>
> > > #include <asm/debugreg.h>
> > > #include <asm/kexec.h>
> > > @@ -4323,12 +4324,16 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
> > > case MSR_IA32_XSS:
> > > if (!vmx_xsaves_supported())
> > > return 1;
> > > +
> > > /*
> > > - * The only supported bit as of Skylake is bit 8, but
> > > - * it is not supported on KVM.
> > > + * Right now, only support XSS_CET_U[bit 11] and
> > > + * XSS_CET_S[bit 12] in MSR_IA32_XSS.
> > > */
> > > - if (data != 0)
> > > +
> > > + if (data & ~(XFEATURE_MASK_SHSTK_USER
> > > + | XFEATURE_MASK_SHSTK_KERNEL))
> >
> > New lines are usually after the operator, e.g.:
> >
> > if (data & ~(XFEATURE_MASK_SHSTK_USER |
> > XFEATURE_MASK_SHSTK_KERNEL))
> >
> > And doesn't this flow need to check that the bits are actually supported?
> Supported on the host and in the guest.
next prev parent reply other threads:[~2019-01-07 14:24 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-12-26 8:15 [PATCH v1 0/8] This patch-set is to enable kvm Guest OS CET support Yang Weijiang
2018-12-26 8:15 ` [PATCH v1 1/8] kvm:vmx Introduce CET related VMCS field definitions Yang Weijiang
2019-01-02 18:09 ` Sean Christopherson
2018-12-26 8:15 ` [PATCH v1 2/8] kvm: Define CR4.CET[bit 23] (master enable bit) for guest OS Yang Weijiang
2018-12-26 8:15 ` [PATCH v1 3/8] kvm:vmx Enable loading CET state bit while guest CR4.CET is being set Yang Weijiang
2018-12-26 8:52 ` Liran Alon
2018-12-27 6:07 ` Yang,Weijiang
2018-12-26 8:15 ` [PATCH v1 4/8] kvm:vmx Pass through host CET related MSRs to Guest Yang Weijiang
2019-01-02 18:18 ` Sean Christopherson
2019-01-02 19:12 ` Jim Mattson
2018-12-26 8:15 ` [PATCH v1 5/8] kvm:x86 Enable MSR_IA32_XSS bit 11 and 12 for CET xsaves/xrstors Yang Weijiang
2019-01-02 18:24 ` Sean Christopherson
2019-01-02 19:19 ` Jim Mattson
2019-01-06 21:17 ` Yang Weijiang [this message]
2018-12-26 8:15 ` [PATCH v1 6/8] kvm:cpuid Add CPUID support for CET xsaves component query Yang Weijiang
2019-01-02 18:49 ` Sean Christopherson
2018-12-26 8:15 ` [PATCH v1 7/8] kvm:cpuid Fix xsaves area size calculation for CPUID.(EAX=0xD,ECX=1) Yang Weijiang
2019-01-02 18:54 ` Sean Christopherson
2018-12-26 8:15 ` [PATCH v1 8/8] kvm:cpuid Report CET SHSTK and IBT support in CPUID.(EAX=0x7,ECX=0) Yang Weijiang
2019-01-02 19:00 ` Sean Christopherson
2019-01-07 16:03 ` Paolo Bonzini
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