From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.6 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 66506C43387 for ; Tue, 8 Jan 2019 19:39:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 2DB7F2063F for ; Tue, 8 Jan 2019 19:39:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1546976348; bh=6cOhFqO/9x5iVXUnGkodK93GH/+rI2u5VVHZ4Oba+Yw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=ZnTZ+rvaWUXPRzURsDYcSayAbVl5+SAgYr9LKAq8I3IzeIAC1ucjo9lNAUGGhAA9M NTTZJ9rp4lWsAutJiUeU8TZcmSPOfqcxE/sKv34OAei8I8V7vU1DPhalWLjBSpKzdm yKY3WqOQfb2rUA/lo6qd4a8upguvRQecv0vq1n1M= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732492AbfAHTjH (ORCPT ); Tue, 8 Jan 2019 14:39:07 -0500 Received: from mail.kernel.org ([198.145.29.99]:43930 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732171AbfAHTfI (ORCPT ); Tue, 8 Jan 2019 14:35:08 -0500 Received: from sasha-vm.mshome.net (c-73-47-72-35.hsd1.nh.comcast.net [73.47.72.35]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 69E342063F; Tue, 8 Jan 2019 19:35:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1546976108; bh=6cOhFqO/9x5iVXUnGkodK93GH/+rI2u5VVHZ4Oba+Yw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=EmV33uABKgbAeeH97GbnflAjaAyB9ss2xoe7cXDB1mWWer2odq3e23OFexhmkCZD9 HkWLDs0RwUdBc2biZaHFklL+xk4K8mNz2C6tCA4lGU0B2JiH09FONHRVrNit6SQ2SH pu8WXTAI3NUA0g5DSNNsOZFQfvRaiEgMvokm7U3I= From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Lucas Stach , Stephen Boyd , Sasha Levin , linux-clk@vger.kernel.org Subject: [PATCH AUTOSEL 4.4 14/28] clk: imx6q: reset exclusive gates on init Date: Tue, 8 Jan 2019 14:34:31 -0500 Message-Id: <20190108193445.124251-14-sashal@kernel.org> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20190108193445.124251-1-sashal@kernel.org> References: <20190108193445.124251-1-sashal@kernel.org> MIME-Version: 1.0 X-Patchwork-Hint: Ignore Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Lucas Stach [ Upstream commit f7542d817733f461258fd3a47d77da35b2d9fc81 ] The exclusive gates may be set up in the wrong way by software running before the clock driver comes up. In that case the exclusive setup is locked in its initial state, as the complementary function can't be activated without disabling the initial setup first. To avoid this lock situation, reset the exclusive gates to the off state and allow the kernel to provide the proper setup. Signed-off-by: Lucas Stach Reviewed-by: Dong Aisheng Signed-off-by: Stephen Boyd Signed-off-by: Sasha Levin --- drivers/clk/imx/clk-imx6q.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c index a0df83e6b84b..46c05c9a9354 100644 --- a/drivers/clk/imx/clk-imx6q.c +++ b/drivers/clk/imx/clk-imx6q.c @@ -239,8 +239,12 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) * lvds1_gate and lvds2_gate are pseudo-gates. Both can be * independently configured as clock inputs or outputs. We treat * the "output_enable" bit as a gate, even though it's really just - * enabling clock output. + * enabling clock output. Initially the gate bits are cleared, as + * otherwise the exclusive configuration gets locked in the setup done + * by software running before the clock driver, with no way to change + * it. */ + writel(readl(base + 0x160) & ~0x3c00, base + 0x160); clk[IMX6QDL_CLK_LVDS1_GATE] = imx_clk_gate_exclusive("lvds1_gate", "lvds1_sel", base + 0x160, 10, BIT(12)); clk[IMX6QDL_CLK_LVDS2_GATE] = imx_clk_gate_exclusive("lvds2_gate", "lvds2_sel", base + 0x160, 11, BIT(13)); -- 2.19.1