From: Stefan Agner <stefan@agner.ch>
To: shawnguo@kernel.org, s.hauer@pengutronix.de
Cc: max.krummenacher@toradex.com, marcel.ziswiler@toradex.com,
dev@pschenker.ch, kernel@pengutronix.de, fabio.estevam@nxp.com,
linux-imx@nxp.com, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, Stefan Agner <stefan@agner.ch>
Subject: [PATCH 1/2] ARM: dts: imx6q: add pmu interrupt-affinity
Date: Fri, 18 Jan 2019 14:59:06 +0100 [thread overview]
Message-ID: <20190118135907.2336-1-stefan@agner.ch> (raw)
Explicitly specify interrupt affinity to avoid HW perfevents
need to guess. This avoids the following error upon boot:
hw perfevents: no interrupt-affinity property for /pmu, guessing.
Specifying all four CPUs shows no aversive effects on i.MX 6Dual
SoCs.
Signed-off-by: Stefan Agner <stefan@agner.ch>
---
arch/arm/boot/dts/imx6q.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 8381d24eff7d..d2c1977c8b16 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -537,6 +537,13 @@
<0x28 0x0000000c>; /* DCIC2_MUX_CTL */
};
+&pmu {
+ interrupt-affinity = <&{/cpus/cpu@0}>,
+ <&{/cpus/cpu@1}>,
+ <&{/cpus/cpu@2}>,
+ <&{/cpus/cpu@3}>;
+};
+
&vpu {
compatible = "fsl,imx6q-vpu", "cnm,coda960";
};
--
2.20.1
next reply other threads:[~2019-01-18 13:59 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-01-18 13:59 Stefan Agner [this message]
2019-01-18 13:59 ` [PATCH 2/2] ARM: dts: imx6dl: " Stefan Agner
2019-01-18 14:12 ` [PATCH 1/2] ARM: dts: imx6q: " Lucas Stach
2019-01-18 15:41 ` Stefan Agner
2019-01-21 9:39 ` Stefan Agner
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