From: Borislav Petkov <bp@alien8.de>
To: Sasha Levin <sashal@kernel.org>
Cc: mchehab@kernel.org, ruizhao@microsoft.com,
linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-kernel@microsoft.com, will.deacon@arm.com,
okaya@kernel.org
Subject: Re: [PATCH] EDAC, dmc520:: add DMC520 EDAC driver
Date: Mon, 21 Jan 2019 13:35:47 +0100 [thread overview]
Message-ID: <20190121123547.GF29166@zn.tnic> (raw)
In-Reply-To: <20190118162324.17123-1-sashal@kernel.org>
On Fri, Jan 18, 2019 at 11:23:24AM -0500, Sasha Levin wrote:
> From: Rui Zhao <ruizhao@microsoft.com>
>
> New driver supports DRAM error detection and correction on DMC520
> controller.
That's this thing, right?
https://developer.arm.com/products/system-ip/memory-controllers/corelink-dmc-520
> Validated on actual hardware:
Which is what exactly?
This looks like a driver for the memory controller IP and that could get
integrated in other platforms so I'd prefer if this driver was called
<your_platform>_edac and the DMC520 was a generic piece of functionality
like the FSL memory controller IP:
mpc85xx_edac_mod-y := fsl_ddr_edac.o mpc85xx_edac.o
obj-$(CONFIG_EDAC_MPC85XX) += mpc85xx_edac_mod.o
layerscape_edac_mod-y := fsl_ddr_edac.o layerscape_edac.o
obj-$(CONFIG_EDAC_LAYERSCAPE) += layerscape_edac_mod.o
Thx.
--
Regards/Gruss,
Boris.
Good mailing practices for 400: avoid top-posting and trim the reply.
next prev parent reply other threads:[~2019-01-21 12:35 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-01-18 16:23 Sasha Levin
2019-01-21 12:35 ` Borislav Petkov [this message]
2019-01-23 18:50 ` Sasha Levin
2019-01-23 19:03 ` Borislav Petkov
2019-01-23 19:09 ` Sasha Levin
2019-01-21 17:09 ` James Morse
[not found] ` <MW2PR2101MB09701C705250DAC025AFC251B3990@MW2PR2101MB0970.namprd21.prod.outlook.com>
2019-01-23 18:36 ` James Morse
2019-01-23 18:46 ` Borislav Petkov
2019-02-05 17:31 ` James Morse
2019-01-23 22:08 ` Rui Zhao
2019-02-05 17:31 ` James Morse
2019-03-06 5:20 ` Rui Zhao
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