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Tue, 22 Jan 2019 04:24:14 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector1-arm-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=6uLI7lEqKNHHcfLRAnRhgjzQTYqLzc3fNgVXDhen49c=; b=qc3O+MeafKKtbwfujh5Lw7UTXZ3YHe0a7q4rDCH+AlPt8P2lq465jdgtdMzeeR4xejy79nLLTVkdcucE/l1rwibza55gwJ6TYJJS8sJe/2+/keSLVjwvlCaYYK0jo1R16QqbEkgoyZiBXCsF/SlL8a2qwqHNpyhBq45lrWufV3o= Received: from DB6PR0801MB1990.eurprd08.prod.outlook.com (10.168.81.21) by DB6PR0801MB1928.eurprd08.prod.outlook.com (10.168.83.136) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1537.28; Tue, 22 Jan 2019 09:24:07 +0000 Received: from DB6PR0801MB1990.eurprd08.prod.outlook.com ([fe80::b9be:3d28:78a2:6e33]) by DB6PR0801MB1990.eurprd08.prod.outlook.com ([fe80::b9be:3d28:78a2:6e33%2]) with mapi id 15.20.1537.031; Tue, 22 Jan 2019 09:24:07 +0000 From: "james qian wang (Arm Technology China)" To: Liviu Dudau , "airlied@linux.ie" , Brian Starkey CC: "Jonathan Chai (Arm Technology China)" , "Julien Yin (Arm Technology China)" , "thomas Sun (Arm Technology China)" , "Lowry Li (Arm Technology China)" , Ayan Halder , "Tiannan Zhu (Arm Technology China)" , "Jin Gao (Arm Technology China)" , "Yiqi Kang (Arm Technology China)" , nd , "malidp@foss.arm.com" , "linux-kernel@vger.kernel.org" , "dri-devel@lists.freedesktop.org" , "james qian wang (Arm Technology China)" Subject: [PATCH v2 4/7] drm/komeda: Add D71 improc and timing_ctrlr Thread-Topic: [PATCH v2 4/7] drm/komeda: Add D71 improc and timing_ctrlr Thread-Index: AQHUsjQ5I/Axu8OgSUmbAN0FI2Xcuw== Date: Tue, 22 Jan 2019 09:24:07 +0000 Message-ID: <20190122092243.21226-5-james.qian.wang@arm.com> References: <20190122092243.21226-1-james.qian.wang@arm.com> In-Reply-To: <20190122092243.21226-1-james.qian.wang@arm.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [113.29.88.7] x-clientproxiedby: SYCPR01CA0039.ausprd01.prod.outlook.com (2603:10c6:10:e::27) To DB6PR0801MB1990.eurprd08.prod.outlook.com (2603:10a6:4:6c::21) x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.17.1 x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1;DB6PR0801MB1928;6:EHdE0uMw48djwwc+GcVTZhHpyrFN3HLLIRZA7f40y7xL7wAbWHHVOgptXYb72T7tGRJ7S+wXqsY0WzoXanq6LqYWdqKRcG6prHqYbo56BXinH45U/KGxlMkATPT0RTL427jdDhnoauUkfMdlUU64D+eankY5IuTMCcdB7Id7Km2QOKiS8jtwAoMAeqIymvMZx/ztRPcCliJzVCjtkk7PqAvZp9okreIwACuJBXWhow3zEqPLhMRUcEwPRP9+xuDMEV/cagQAEGcC/rB5xkfvxn1Kdlj1fZpNfV7ylGmPg+URfgs6h/VMTzai9F5S2AhBcgDFhPSaTaSO4otrzH1YsQHAmPfScVE2lYjuMtNOLg4QmiMiz2Ptrsb+kpOc7B9lcQnFJzi4Ln066/qrV7gQF2UXtPDJQRXLhOlxQUUSiyGFzoYId3+RTc/zdAA5DWtWWz5QNJ9dX3jBNsM4n4WBpA==;5:/GfYOzGKKMjDx/P4DzbCmCXUAgewNWZ7KE2dK0+tFwu66Y7tmUYuU9JpCUJ0lPau5bxntf07Tzq3WVxt8ZmLVS5XyKE6+o3weSS2otBLxWSdKXT6ElbMe5GW9b9xXFOPDgfNW5iXHmZ6VT+N6BLVk/N2rxTxP34U9l1noFjptDqCuuqbZyJ/4BpAA5+hhDeIZRegAm1RxOJ2erIci1HxFA==;7:F6gzNb66VYR47npZs0AXSb1JeFB5wxuY2BA/0RHEOtlxYInIxqbf7XbjABGL51xJbVak+PsVMT5Wcf/EhM0RM+nJnj63XnTof0uNJv3yTuDk1gCudWn1QaewUxPJjIxLoFYNDyGPuKgfkX+7GGRQkw== x-ms-office365-filtering-correlation-id: e71ea495-2498-4dc6-6c6d-08d6804b5c00 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0;PCL:0;RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(7168020)(4627221)(201703031133081)(201702281549075)(8990200)(5600109)(711020)(4618075)(2017052603328)(7153060)(7193020);SRVR:DB6PR0801MB1928; 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x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: ASdPqUdhVJRVi1yVVxD8hsxluxF07Gb525Byyjv6L1/NlqozXsNQpVvvUUgmxLrrbHfW46PmSIWkeG4CdLXe+ixyqlykoqGOlzvf2VUieG+ruBSqfq4n1T3V+9ZHUmYPHtFGo27PQbqa6Ay37wFpcywwkZBMei1v9eEL1yeYWUCWPpmrxtip/UUcbkUYdGCpqyN66kRI9ZYKdTvZCPtz30tzs6U9Dw77JKkV+VKmwHrFIZSHTVlHWU7FmS3x33OtzWNNAquKrkrcbbuYsk46sJUuCGNAW9YsysUAqWiAKMSNGcjtSv6elcD1HiGK2Ica0WOnt60mEE52HUhGtJsVlFPs7dQMRDYHDBiKOGLQrHqKOxTbUc9nFBhjsAeNmX/XWt3t6R8riW8pFlzb+MC7WK2gQPZlsyVcj4QjtwBBt1Q= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-Network-Message-Id: e71ea495-2498-4dc6-6c6d-08d6804b5c00 X-MS-Exchange-CrossTenant-originalarrivaltime: 22 Jan 2019 09:23:59.2687 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB6PR0801MB1928 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: "james qian wang (Arm Technology China)" Add and initialize improc and timing_ctrlr according to D71 capablitites v2: Rebase. Signed-off-by: James Qian Wang (Arm Technology China) --- .../arm/display/komeda/d71/d71_component.c | 111 +++++++++++++++++- .../gpu/drm/arm/display/komeda/komeda_kms.h | 2 + .../drm/arm/display/komeda/komeda_pipeline.h | 7 ++ 3 files changed, 118 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/arm/display/komeda/d71/d71_component.c b/drive= rs/gpu/drm/arm/display/komeda/d71/d71_component.c index 401053ef0a53..095779964518 100644 --- a/drivers/gpu/drm/arm/display/komeda/d71/d71_component.c +++ b/drivers/gpu/drm/arm/display/komeda/d71/d71_component.c @@ -282,18 +282,125 @@ static int d71_compiz_init(struct d71_dev *d71, return 0; } =20 +static void d71_improc_update(struct komeda_component *c, + struct komeda_component_state *state) +{ + struct komeda_improc_state *st =3D to_improc_st(state); + u32 __iomem *reg =3D c->reg; + u32 index, input_hw_id; + + for_each_changed_input(state, index) { + input_hw_id =3D state->active_inputs & BIT(index) ? + to_d71_input_id(&state->inputs[index]) : 0; + malidp_write32(reg, BLK_INPUT_ID0 + index * 4, input_hw_id); + } + + malidp_write32(reg, BLK_SIZE, HV_SIZE(st->hsize, st->vsize)); +} + +struct komeda_component_funcs d71_improc_funcs =3D { + .update =3D d71_improc_update, + .disable =3D d71_component_disable, +}; + static int d71_improc_init(struct d71_dev *d71, struct block_header *blk, u32 __iomem *reg) { - DRM_DEBUG("Detect D71_improc.\n"); + struct komeda_component *c; + struct komeda_improc *improc; + u32 pipe_id, comp_id, value; + + get_resources_id(blk->block_info, &pipe_id, &comp_id); + + c =3D komeda_component_add(&d71->pipes[pipe_id]->base, sizeof(*improc), + comp_id, + BLOCK_INFO_INPUT_ID(blk->block_info), + &d71_improc_funcs, IPS_NUM_INPUT_IDS, + get_valid_inputs(blk), + IPS_NUM_OUTPUT_IDS, reg, "DOU%d_IPS", pipe_id); + if (IS_ERR(c)) { + DRM_ERROR("Failed to add improc component\n"); + return PTR_ERR(c); + } + + improc =3D to_improc(c); + improc->supported_color_depths =3D BIT(8) | BIT(10); + improc->supported_color_formats =3D DRM_COLOR_FORMAT_RGB444 | + DRM_COLOR_FORMAT_YCRCB444 | + DRM_COLOR_FORMAT_YCRCB422; + value =3D malidp_read32(reg, BLK_INFO); + if (value & IPS_INFO_CHD420) + improc->supported_color_formats |=3D DRM_COLOR_FORMAT_YCRCB420; + + improc->supports_csc =3D true; + improc->supports_gamma =3D true; =20 return 0; } =20 +static void d71_timing_ctrlr_disable(struct komeda_component *c) +{ + malidp_write32_mask(c->reg, BLK_CONTROL, BS_CTRL_EN, 0); +} + +static void d71_timing_ctrlr_update(struct komeda_component *c, + struct komeda_component_state *state) +{ + struct drm_crtc_state *crtc_st =3D state->crtc->state; + u32 __iomem *reg =3D c->reg; + struct videomode vm; + u32 value; + + drm_display_mode_to_videomode(&crtc_st->adjusted_mode, &vm); + + malidp_write32(reg, BS_ACTIVESIZE, HV_SIZE(vm.hactive, vm.vactive)); + malidp_write32(reg, BS_HINTERVALS, BS_H_INTVALS(vm.hfront_porch, + vm.hback_porch)); + malidp_write32(reg, BS_VINTERVALS, BS_V_INTVALS(vm.vfront_porch, + vm.vback_porch)); + + value =3D BS_SYNC_VSW(vm.vsync_len) | BS_SYNC_HSW(vm.hsync_len); + value |=3D vm.flags & DISPLAY_FLAGS_VSYNC_HIGH ? BS_SYNC_VSP : 0; + value |=3D vm.flags & DISPLAY_FLAGS_HSYNC_HIGH ? BS_SYNC_HSP : 0; + malidp_write32(reg, BS_SYNC, value); + + malidp_write32(reg, BS_PROG_LINE, D71_DEFAULT_PREPRETCH_LINE - 1); + malidp_write32(reg, BS_PREFETCH_LINE, D71_DEFAULT_PREPRETCH_LINE); + + /* configure bs control register */ + value =3D BS_CTRL_EN | BS_CTRL_VM; + + malidp_write32(reg, BLK_CONTROL, value); +} + +struct komeda_component_funcs d71_timing_ctrlr_funcs =3D { + .update =3D d71_timing_ctrlr_update, + .disable =3D d71_timing_ctrlr_disable, +}; + static int d71_timing_ctrlr_init(struct d71_dev *d71, struct block_header *blk, u32 __iomem *reg) { - DRM_DEBUG("Detect D71_timing_ctrlr.\n"); + struct komeda_component *c; + struct komeda_timing_ctrlr *ctrlr; + u32 pipe_id, comp_id; + + get_resources_id(blk->block_info, &pipe_id, &comp_id); + + c =3D komeda_component_add(&d71->pipes[pipe_id]->base, sizeof(*ctrlr), + KOMEDA_COMPONENT_TIMING_CTRLR, + BLOCK_INFO_INPUT_ID(blk->block_info), + &d71_timing_ctrlr_funcs, + 1, BIT(KOMEDA_COMPONENT_IPS0 + pipe_id), + BS_NUM_OUTPUT_IDS, reg, "DOU%d_BS", pipe_id); + if (IS_ERR(c)) { + DRM_ERROR("Failed to add display_ctrl component\n"); + return PTR_ERR(c); + } + + ctrlr =3D to_ctrlr(c); + + ctrlr->supports_dual_link =3D true; =20 return 0; } diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_kms.h b/drivers/gpu/= drm/arm/display/komeda/komeda_kms.h index f13666004a42..f519a4c587e6 100644 --- a/drivers/gpu/drm/arm/display/komeda/komeda_kms.h +++ b/drivers/gpu/drm/arm/display/komeda/komeda_kms.h @@ -11,6 +11,8 @@ #include #include #include +#include