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Wed, 23 Jan 2019 15:23:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=akkea.ca; s=mail; t=1548257027; bh=gxfqLH8vJS7wvyDzrJWQ+wEpfRbNkKqz+gu1K4Y4fcg=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=cGLTWpOU3JjGqJwlXT7vz+tCoJt47/6q9m83Zm9fa0WDSK2j4ncFkzDgdD9nc2T9P giLb1tU4C777qDM2+0GJmu4klH73bm+x9EwTkO6IYDvatHGLB8+4cf2LDGFJ4JEwje o0Hd6/WwGCHfj6qCIOeGnVypr2wvkY+rV0gjTJpM= From: "Angus Ainslie (Purism)" To: angus@akkea.ca Cc: angus.ainslie@puri.sm, Vinod Koul , dmaengine@vger.kernel.org, NXP Linux Team , Pengutronix Kernel Team , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Lucas Stach , Daniel Baluta Subject: [PATCH v3 5/5] imx8mq.dtsi: add the sdma nodes Date: Wed, 23 Jan 2019 08:23:10 -0700 Message-Id: <20190123152310.11680-6-angus@akkea.ca> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190123152310.11680-1-angus@akkea.ca> References: <20190120023150.17138-1-angus@akkea.ca> <20190123152310.11680-1-angus@akkea.ca> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add the sdma nodes to the base devicetree for the imx8mq Signed-off-by: Angus Ainslie (Purism) --- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 31 +++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index c0402375e7c1..4397992fd021 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -336,6 +336,19 @@ clocks = <&clk IMX8MQ_CLK_WDOG3_ROOT>; status = "disabled"; }; + + sdma2: sdma@302c0000 { + compatible = "fsl,imx8mq-sdma", "fsl,imx7d-sdma"; + reg = <0x302c0000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MQ_CLK_SDMA2_ROOT>, + <&clk IMX8MQ_CLK_SDMA2_ROOT>; + clock-names = "ipg", "ahb"; + #dma-cells = <3>; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; + fsl,ratio-1-1; + status = "disabled"; + }; }; bus@30400000 { /* AIPS2 */ @@ -370,6 +383,8 @@ clocks = <&clk IMX8MQ_CLK_UART3_ROOT>, <&clk IMX8MQ_CLK_UART3_ROOT>; clock-names = "ipg", "per"; + dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -381,6 +396,8 @@ clocks = <&clk IMX8MQ_CLK_UART2_ROOT>, <&clk IMX8MQ_CLK_UART2_ROOT>; clock-names = "ipg", "per"; + dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -432,6 +449,8 @@ clocks = <&clk IMX8MQ_CLK_UART4_ROOT>, <&clk IMX8MQ_CLK_UART4_ROOT>; clock-names = "ipg", "per"; + dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -465,6 +484,18 @@ status = "disabled"; }; + sdma1: sdma@30bd0000 { + compatible = "fsl,imx8mq-sdma", "fsl,imx7d-sdma"; + reg = <0x30bd0000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MQ_CLK_SDMA1_ROOT>, + <&clk IMX8MQ_CLK_AHB>; + clock-names = "ipg", "ahb"; + #dma-cells = <3>; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; + status = "disabled"; + }; + fec1: ethernet@30be0000 { compatible = "fsl,imx8mq-fec", "fsl,imx6sx-fec"; reg = <0x30be0000 0x10000>; -- 2.17.1