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received-spf: None (protection.outlook.com: amd.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: s2/8Uwp9ymuPD5PE6kZgobUBnVPoCqphW9AgJqQ2ixIjVuqf0G3rWZbY7hr+5iZExJLXWp9l9SWMwqFAXDMMkrGvhL6DZgsd3PvniRtbfCHHDQ653Ro0wRoYHSWwTHgHvsueIsntvqHrUOcnXaL8h3obVXgezEhi/St/xfhzvKd78LM1rxtcLvbfC0+h4GjZx40sIiytYLsJkrln7Vu6OSjNbd4BnqtA/ZbBFIfQDmjxNjtuWRwiTfovfScOXAHbQHQC5O8BxpD4pvreJwKSaP3S9sM960whxdoB7k6qzcYJ3Uj/VxgTO+fpgr+jO0GWqumahtMHsxx9V13XxZcpDcu4AW/CAJ8dH10fHSTyyQh19evJ2DIalWoY++6MJd4O83Eae5eUSn+Lt1o28JZMvUUkhFFbgPFXyCctfHbu+IU= Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: d0054f87-eaa2-4258-d467-08d6889869a2 X-MS-Exchange-CrossTenant-originalarrivaltime: 01 Feb 2019 22:55:50.3185 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN7PR12MB2628 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Yazen Ghannam Add the (HWID, MCATYPE) tuples and names for the new MP5, NBIO, and PCIE SMCA bank types. Also, add their respective error descriptions to edac_mce_amd. Signed-off-by: Yazen Ghannam --- arch/x86/include/asm/mce.h | 3 +++ arch/x86/kernel/cpu/mce/amd.c | 12 ++++++++++++ drivers/edac/mce_amd.c | 32 ++++++++++++++++++++++++++++++++ 3 files changed, 47 insertions(+) diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h index c1a812bd5a27..91b65d859ca8 100644 --- a/arch/x86/include/asm/mce.h +++ b/arch/x86/include/asm/mce.h @@ -312,6 +312,9 @@ enum smca_bank_types { SMCA_PB, /* Parameter Block */ SMCA_PSP, /* Platform Security Processor */ SMCA_SMU, /* System Management Unit */ + SMCA_MP5, /* Microprocessor 5 Unit */ + SMCA_NBIO, /* Northbridge IO Unit */ + SMCA_PCIE, /* PCI Express Unit */ N_SMCA_BANK_TYPES }; =20 diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index ed3327342b40..00f60b8c7e4f 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -93,6 +93,9 @@ static struct smca_bank_name smca_names[] =3D { [SMCA_PB] =3D { "param_block", "Parameter Block" }, [SMCA_PSP] =3D { "psp", "Platform Security Processor" }, [SMCA_SMU] =3D { "smu", "System Management Unit" }, + [SMCA_MP5] =3D { "mp5", "Microprocessor 5 Unit" }, + [SMCA_NBIO] =3D { "nbio", "Northbridge IO Unit" }, + [SMCA_PCIE] =3D { "pcie", "PCI Express Unit" }, }; =20 static u32 smca_bank_addrs[MAX_NR_BANKS][NR_BLOCKS] __ro_after_init =3D @@ -162,6 +165,15 @@ static struct smca_hwid smca_hwid_mcatypes[] =3D { =20 /* System Management Unit MCA type */ { SMCA_SMU, HWID_MCATYPE(0x01, 0x0), 0x1 }, + + /* Microprocessor 5 Unit MCA type */ + { SMCA_MP5, HWID_MCATYPE(0x01, 0x2), 0x3FF }, + + /* Northbridge IO Unit MCA type */ + { SMCA_NBIO, HWID_MCATYPE(0x18, 0x0), 0x1F }, + + /* PCI Express Unit MCA type */ + { SMCA_PCIE, HWID_MCATYPE(0x46, 0x0), 0x1F }, }; =20 struct smca_bank smca_banks[MAX_NR_BANKS]; diff --git a/drivers/edac/mce_amd.c b/drivers/edac/mce_amd.c index c605089d899f..5ab4ab3f0ce6 100644 --- a/drivers/edac/mce_amd.c +++ b/drivers/edac/mce_amd.c @@ -285,6 +285,35 @@ static const char * const smca_smu_mce_desc[] =3D { "SMU RAM ECC or parity error", }; =20 +static const char * const smca_mp5_mce_desc[] =3D { + "High SRAM ECC or parity error", + "Low SRAM ECC or parity error", + "Data Cache Bank A ECC or parity error", + "Data Cache Bank B ECC or parity error", + "Data Tag Cache Bank A ECC or parity error", + "Data Tag Cache Bank B ECC or parity error", + "Instruction Cache Bank A ECC or parity error", + "Instruction Cache Bank B ECC or parity error", + "Instruction Tag Cache Bank A ECC or parity error", + "Instruction Tag Cache Bank B ECC or parity error", +}; + +static const char * const smca_nbio_mce_desc[] =3D { + "ECC or Parity error", + "PCIE error", + "SDP ErrEvent error", + "SDP Egress Poison Error", + "IOHC Internal Poison Error", +}; + +static const char * const smca_pcie_mce_desc[] =3D { + "CCIX PER Message logging", + "CCIX Read Response with Status: Non-Data Error", + "CCIX Write Response with Status: Non-Data Error", + "CCIX Read Response with Status: Data Error", + "CCIX Non-okay write response with data error", +}; + struct smca_mce_desc { const char * const *descs; unsigned int num_descs; @@ -304,6 +333,9 @@ static struct smca_mce_desc smca_mce_descs[] =3D { [SMCA_PB] =3D { smca_pb_mce_desc, ARRAY_SIZE(smca_pb_mce_desc) }, [SMCA_PSP] =3D { smca_psp_mce_desc, ARRAY_SIZE(smca_psp_mce_desc) }, [SMCA_SMU] =3D { smca_smu_mce_desc, ARRAY_SIZE(smca_smu_mce_desc) }, + [SMCA_MP5] =3D { smca_mp5_mce_desc, ARRAY_SIZE(smca_mp5_mce_desc) }, + [SMCA_NBIO] =3D { smca_nbio_mce_desc, ARRAY_SIZE(smca_nbio_mce_desc) }, + [SMCA_PCIE] =3D { smca_pcie_mce_desc, ARRAY_SIZE(smca_pcie_mce_desc) }, }; =20 static bool f12h_mc0_mce(u16 ec, u8 xec) --=20 2.17.1