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[90.86.125.223]) by smtp.gmail.com with ESMTPSA id q9sm11197506wrv.26.2019.02.04.09.18.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 04 Feb 2019 09:18:12 -0800 (PST) From: Bartosz Golaszewski To: Sekhar Nori , Kevin Hilman , Daniel Lezcano , Rob Herring , Mark Rutland , Thomas Gleixner Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Bartosz Golaszewski Subject: [PATCH v2 05/12] ARM: davinci: da850: switch to using the clocksource driver Date: Mon, 4 Feb 2019 18:17:50 +0100 Message-Id: <20190204171757.32073-6-brgl@bgdev.pl> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190204171757.32073-1-brgl@bgdev.pl> References: <20190204171757.32073-1-brgl@bgdev.pl> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Bartosz Golaszewski We now have a proper clocksource driver for davinci. Switch the platform to using it. Signed-off-by: Bartosz Golaszewski --- arch/arm/mach-davinci/da850.c | 56 ++++++++++++++--------------------- 1 file changed, 22 insertions(+), 34 deletions(-) diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c index beb34ee42e3a..66c2ffd4885b 100644 --- a/arch/arm/mach-davinci/da850.c +++ b/arch/arm/mach-davinci/da850.c @@ -34,7 +34,8 @@ #include #include #include -#include + +#include #include "mux.h" @@ -436,38 +437,24 @@ static struct davinci_id da850_ids[] = { }, }; -static struct davinci_timer_instance da850_timer_instance[4] = { - { - .base = DA8XX_TIMER64P0_BASE, - .bottom_irq = IRQ_DA8XX_TINT12_0, - .top_irq = IRQ_DA8XX_TINT34_0, - }, - { - .base = DA8XX_TIMER64P1_BASE, - .bottom_irq = IRQ_DA8XX_TINT12_1, - .top_irq = IRQ_DA8XX_TINT34_1, - }, - { - .base = DA850_TIMER64P2_BASE, - .bottom_irq = IRQ_DA850_TINT12_2, - .top_irq = IRQ_DA850_TINT34_2, - }, - { - .base = DA850_TIMER64P3_BASE, - .bottom_irq = IRQ_DA850_TINT12_3, - .top_irq = IRQ_DA850_TINT34_3, +static const struct davinci_timer_cfg da850_timer_cfg = { + .reg = { + .start = DA8XX_TIMER64P0_BASE, + .end = DA8XX_TIMER64P0_BASE + SZ_4K, + .flags = IORESOURCE_MEM, }, -}; - -/* - * T0_BOT: Timer 0, bottom : Used for clock_event - * T0_TOP: Timer 0, top : Used for clocksource - * T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer - */ -static struct davinci_timer_info da850_timer_info = { - .timers = da850_timer_instance, - .clockevent_id = T0_BOT, - .clocksource_id = T0_TOP, + .irq = { + { + .start = IRQ_DA8XX_TINT12_0, + .end = IRQ_DA8XX_TINT12_0, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_DA8XX_TINT34_0, + .end = IRQ_DA8XX_TINT34_0, + .flags = IORESOURCE_IRQ, + } + } }; #ifdef CONFIG_CPU_FREQ @@ -742,7 +729,6 @@ static const struct davinci_soc_info davinci_soc_info_da850 = { .intc_type = DAVINCI_INTC_TYPE_CP_INTC, .intc_irq_prios = da850_default_priorities, .intc_irq_num = DA850_N_CP_INTC_IRQ, - .timer_info = &da850_timer_info, .emac_pdata = &da8xx_emac_pdata, .sram_dma = DA8XX_SHARED_RAM_BASE, .sram_len = SZ_128K, @@ -765,6 +751,7 @@ void __init da850_init_time(void) void __iomem *pll0; struct regmap *cfgchip; struct clk *clk; + int rv; clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DA850_REF_FREQ); @@ -779,7 +766,8 @@ void __init da850_init_time(void) return; } - davinci_timer_init(clk); + rv = davinci_timer_register(clk, &da850_timer_cfg); + WARN(rv, "Unable to register the timer: %d\n", rv); } static struct resource da850_pll1_resources[] = { -- 2.20.1