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Tue, 12 Feb 2019 21:24:30 +0000 From: "Ghannam, Yazen" To: "linux-edac@vger.kernel.org" CC: "Ghannam, Yazen" , "linux-kernel@vger.kernel.org" , "bp@suse.de" Subject: [PATCH 2/2] EDAC/mce_amd: Decode MCA_STATUS in bit definition order Thread-Topic: [PATCH 2/2] EDAC/mce_amd: Decode MCA_STATUS in bit definition order Thread-Index: AQHUwxlW2N5u0SxnrECM32V1r2S92A== Date: Tue, 12 Feb 2019 21:24:29 +0000 Message-ID: <20190212212417.107049-2-Yazen.Ghannam@amd.com> References: <20190212212417.107049-1-Yazen.Ghannam@amd.com> In-Reply-To: <20190212212417.107049-1-Yazen.Ghannam@amd.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: SN6PR02CA0015.namprd02.prod.outlook.com (2603:10b6:805:a2::28) To BN7PR12MB2593.namprd12.prod.outlook.com (2603:10b6:408:28::31) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Yazen.Ghannam@amd.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.17.1 x-originating-ip: [165.204.77.1] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: e7656648-3396-4c1c-c740-08d69130790a x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0;PCL:0;RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600110)(711020)(4605077)(4618075)(2017052603328)(7153060)(7193020);SRVR:BN7PR12MB2659; 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received-spf: None (protection.outlook.com: amd.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: MQJc+L5Xh3U+U4yM99nBaeHCEW0n2QVCXzvxF1vD9A0FKjaNo2N3BqSKACQ/SQ8Rln5Hi1Gcl4UM/VQ4wmOcZiP6qenbhjFRzyliXheAdEl84MHytF9dQPMxZKdrmDnbvNRb6gOxCaT7dz+XSUA/+/GwcyBy6mALw45Wor259MHZIVekT7wXTDhey7oPiqd6Qfeq2olP/x+0gSEcHSoyC4UW4k825W7a7AvMCvI7RN4T1mi7NYvgCNQ06/HsU6QBT8YRWcut311i9kdw3dyyMDcKFPQuncQLoGCuALyZzE7e47N3NxO5Xc5ZgzVPNzyJcrz7FRb7DgskG/aKa5DPGkV7lArXmSsUFrZ997WffhBdRkipRcrhfP+IQb3nuCJX1AepV6jx6AhBqnXCpu8hQsxHhXjLTYONUgHeUzcD+qM= Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: e7656648-3396-4c1c-c740-08d69130790a X-MS-Exchange-CrossTenant-originalarrivaltime: 12 Feb 2019 21:24:29.0738 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN7PR12MB2659 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Yazen Ghannam Reorder how we decode the bits in MCA_STATUS to follow how their defined in the register. The order is as follows: Bit : Decode 61 : UC 59 : MiscV 58 : AddrV 57 : PCC 55 : TCC 53 : SyndV 46 : CECC 45 : UECC 44 : Deferred 43 : Poison 40 : Scrub Signed-off-by: Yazen Ghannam --- drivers/edac/mce_amd.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/edac/mce_amd.c b/drivers/edac/mce_amd.c index b349c22bb386..0a1814dad6cf 100644 --- a/drivers/edac/mce_amd.c +++ b/drivers/edac/mce_amd.c @@ -1051,26 +1051,18 @@ amd_decode_mce(struct notifier_block *nb, unsigned = long val, void *data) ((m->status & MCI_STATUS_UC) ? "UE" : (m->status & MCI_STATUS_DEFERRED) ? "-" : "CE"), ((m->status & MCI_STATUS_MISCV) ? "MiscV" : "-"), - ((m->status & MCI_STATUS_PCC) ? "PCC" : "-"), - ((m->status & MCI_STATUS_ADDRV) ? "AddrV" : "-")); - - if (fam >=3D 0x15) { - pr_cont("|%s", (m->status & MCI_STATUS_DEFERRED ? "Deferred" : "-")); - - /* F15h, bank4, bit 43 is part of McaStatSubCache. */ - if (fam !=3D 0x15 || m->bank !=3D 4) - pr_cont("|%s", (m->status & MCI_STATUS_POISON ? "Poison" : "-")); - } + ((m->status & MCI_STATUS_ADDRV) ? "AddrV" : "-"), + ((m->status & MCI_STATUS_PCC) ? "PCC" : "-")); =20 if (boot_cpu_has(X86_FEATURE_SMCA)) { u32 low, high; u32 addr =3D MSR_AMD64_SMCA_MCx_CONFIG(m->bank); =20 - pr_cont("|%s", ((m->status & MCI_STATUS_SYNDV) ? "SyndV" : "-")); - if (!rdmsr_safe(addr, &low, &high) && (low & MCI_CONFIG_MCAX)) pr_cont("|%s", ((m->status & MCI_STATUS_TCC) ? "TCC" : "-")); + + pr_cont("|%s", ((m->status & MCI_STATUS_SYNDV) ? "SyndV" : "-")); } =20 /* do the two bits[14:13] together */ @@ -1078,6 +1070,14 @@ amd_decode_mce(struct notifier_block *nb, unsigned l= ong val, void *data) if (ecc) pr_cont("|%sECC", ((ecc =3D=3D 2) ? "C" : "U")); =20 + if (fam >=3D 0x15) { + pr_cont("|%s", (m->status & MCI_STATUS_DEFERRED ? "Deferred" : "-")); + + /* F15h, bank4, bit 43 is part of McaStatSubCache. */ + if (fam !=3D 0x15 || m->bank !=3D 4) + pr_cont("|%s", (m->status & MCI_STATUS_POISON ? "Poison" : "-")); + } + if (fam >=3D 0x17) pr_cont("|%s", (m->status & MCI_STATUS_SCRUB ? "Scrub" : "-")); =20 --=20 2.17.1