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[68.168.130.77]) by smtp.gmail.com with ESMTPSA id b15sm8159128pfj.44.2019.02.14.05.09.34 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 14 Feb 2019 05:09:34 -0800 (PST) From: Yangtao Li To: maxime.ripard@bootlin.com, wens@csie.org, robh+dt@kernel.org Cc: mark.rutland@arm.com, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Yangtao Li Subject: [PATCH 4/4] arm64: dts: allwinner: h6: Add CPU Operating Performance Points table Date: Thu, 14 Feb 2019 08:09:10 -0500 Message-Id: <20190214130910.9201-5-tiny.windzz@gmail.com> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20190214130910.9201-1-tiny.windzz@gmail.com> References: <20190214130910.9201-1-tiny.windzz@gmail.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add an OPP (Operating Performance Points) table for the CPU cores to enable DVFS (Dynamic Voltage & Frequency Scaling) on the H6. This information comes from github. Signed-off-by: Yangtao Li --- arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 61 ++++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi index 57a1390ecdc2..46a4a69eb38f 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi @@ -28,6 +28,8 @@ enable-method = "psci"; clocks = <&ccu CLK_CPUX>; clock-latency-ns = <244144>; /* 8 32k periods */ + operating-points-v2 = <&cpu_opp_table>; + #cooling-cells = <2>; }; cpu1: cpu@1 { @@ -37,6 +39,8 @@ enable-method = "psci"; clocks = <&ccu CLK_CPUX>; clock-latency-ns = <244144>; /* 8 32k periods */ + operating-points-v2 = <&cpu_opp_table>; + #cooling-cells = <2>; }; cpu2: cpu@2 { @@ -46,6 +50,8 @@ enable-method = "psci"; clocks = <&ccu CLK_CPUX>; clock-latency-ns = <244144>; /* 8 32k periods */ + operating-points-v2 = <&cpu_opp_table>; + #cooling-cells = <2>; }; cpu3: cpu@3 { @@ -55,6 +61,61 @@ enable-method = "psci"; clocks = <&ccu CLK_CPUX>; clock-latency-ns = <244144>; /* 8 32k periods */ + operating-points-v2 = <&cpu_opp_table>; + #cooling-cells = <2>; + }; + }; + + cpu_opp_table: opp_table { + compatible = "operating-points-v2"; + opp-shared; + + opp@480000000 { + opp-hz = /bits/ 64 <480000000>; + opp-microvolt = <800000 800000 880000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp@720000000 { + opp-hz = /bits/ 64 <720000000>; + opp-microvolt = <800000 800000 880000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp@816000000 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <800000 800000 880000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp@888000000 { + opp-hz = /bits/ 64 <888000000>; + opp-microvolt = <800000 800000 940000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp@1080000000 { + opp-hz = /bits/ 64 <1080000000>; + opp-microvolt = <840000 840000 1060000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp@1320000000 { + opp-hz = /bits/ 64 <1320000000>; + opp-microvolt = <900000 900000 1160000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp@1488000000 { + opp-hz = /bits/ 64 <1488000000>; + opp-microvolt = <960000 960000 1160000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp@1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <1060000 1060000 1160000>; + clock-latency-ns = <244144>; /* 8 32k periods */ }; }; -- 2.17.0