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[73.242.244.99]) by smtp.gmail.com with ESMTPSA id k64sm2297550itb.7.2019.02.19.21.18.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 19 Feb 2019 21:18:10 -0800 (PST) From: George Hilliard To: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org, Neil Brown , George Hilliard Subject: [PATCH 05/10] staging: mt7621-mmc: Use pinctrl subsystem to select SDXC pin mode Date: Tue, 19 Feb 2019 22:17:49 -0700 Message-Id: <20190220051754.12195-6-thirtythreeforty@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190220051754.12195-1-thirtythreeforty@gmail.com> References: <20190220051754.12195-1-thirtythreeforty@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The driver previously grabbed the SD pins for itself, ignoring the pin controller. Replace this direct register access with appropriate calls to the pinctrl subsystem. This also allows this driver to work on related devices that have a different pin controller mapping, such as the MT7688. The hardcoded bit index was incorrect on that device. This change could break SD controller functionality on existing devices whose device trees do not specify a pin controller and state for the SD node. Signed-off-by: George Hilliard --- drivers/staging/mt7621-mmc/sd.c | 28 ++++++++++++++++++++++------ 1 file changed, 22 insertions(+), 6 deletions(-) diff --git a/drivers/staging/mt7621-mmc/sd.c b/drivers/staging/mt7621-mmc/sd.c index a7c7ec0d7bbb..97ed7510e96d 100644 --- a/drivers/staging/mt7621-mmc/sd.c +++ b/drivers/staging/mt7621-mmc/sd.c @@ -38,6 +38,7 @@ #include #include #include +#include #include #include @@ -1599,6 +1600,8 @@ static int msdc_drv_probe(struct platform_device *pdev) struct msdc_host *host; struct msdc_hw *hw; int ret; + struct pinctrl *pctrl; + struct pinctrl_state *pins_default; hw = &msdc0_hw; @@ -1671,6 +1674,25 @@ static int msdc_drv_probe(struct platform_device *pdev) host->mrq = NULL; + /* Read pin control settings from device tree */ + pctrl = devm_pinctrl_get(&pdev->dev); + if (IS_ERR(pctrl)) { + ret = PTR_ERR(pctrl); + dev_err(&pdev->dev, "Cannot find pinctrl in device tree\n"); + goto host_free; + } + + pins_default = pinctrl_lookup_state(pctrl, PINCTRL_STATE_DEFAULT); + if (IS_ERR(pins_default)) { + ret = PTR_ERR(pins_default); + dev_err(&pdev->dev, "Cannot find pinctrl state default\n"); + goto host_free; + } + + ret = pinctrl_select_state(pctrl, pins_default); + if (ret < 0) + dev_warn(&pdev->dev, "Cannot select pinctrl state\n"); + dma_coerce_mask_and_coherent(mmc_dev(mmc), DMA_BIT_MASK(32)); /* using dma_alloc_coherent*/ /* todo: using 1, for all 4 slots */ @@ -1822,12 +1844,6 @@ static struct platform_driver mt_msdc_driver = { static int __init mt_msdc_init(void) { int ret; - u32 reg; - - // Set the pins for sdxc to sdxc mode - //FIXME: this should be done by pinctl and not by the sd driver - reg = readl((void __iomem *)(RALINK_SYSCTL_BASE + 0x60)) & ~(0x3 << 18); - writel(reg, (void __iomem *)(RALINK_SYSCTL_BASE + 0x60)); ret = platform_driver_register(&mt_msdc_driver); if (ret) { -- 2.20.1