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[45.79.96.158]) by smtp.gmail.com with ESMTPSA id 186sm2964629pga.36.2019.02.22.04.49.09 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 22 Feb 2019 04:49:11 -0800 (PST) Date: Fri, 22 Feb 2019 20:49:06 +0800 From: Leo Yan To: Marc Zyngier Cc: Christoffer Dall , Catalin Marinas , Will Deacon , Mark Rutland , James Morse , Andre Przywara , Jun Yao , Paolo Bonzini , linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, linux-kernel@vger.kernel.org Subject: Re: [PATCH v1 2/4] KVM: arm/arm64: vgic: Improve comment on kvm_vgic_inject_irq Message-ID: <20190222124906.GB845@leoy-ThinkPad-X240s> References: <20190222082327.3312-1-leo.yan@linaro.org> <20190222082327.3312-3-leo.yan@linaro.org> <20190222083756.359523ca@why.wild-wind.fr.eu.org> <20190222085439.GA845@leoy-ThinkPad-X240s> <20190222093923.09e36583@why.wild-wind.fr.eu.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20190222093923.09e36583@why.wild-wind.fr.eu.org> User-Agent: Mutt/1.9.4 (2018-02-28) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Feb 22, 2019 at 09:39:23AM +0000, Marc Zyngier wrote: [...] > > > > diff --git a/virt/kvm/arm/vgic/vgic.c b/virt/kvm/arm/vgic/vgic.c > > > > index 7cfdfbc910e0..79fe64c15051 100644 > > > > --- a/virt/kvm/arm/vgic/vgic.c > > > > +++ b/virt/kvm/arm/vgic/vgic.c > > > > @@ -394,7 +394,7 @@ bool vgic_queue_irq_unlock(struct kvm *kvm, struct vgic_irq *irq, > > > > /** > > > > * kvm_vgic_inject_irq - Inject an IRQ from a device to the vgic > > > > * @kvm: The VM structure pointer > > > > - * @cpuid: The CPU for PPIs > > > > + * @cpuid: The CPU for PPIs and SPIs > > > > * @intid: The INTID to inject a new state to. > > > > * @level: Edge-triggered: true: to trigger the interrupt > > > > * false: to ignore the call > > > > > > What does the CPU mean for SPIs? By definition, the routing of an SPI > > > is defined by the distributor configuration. > > > > In the code, KVM injects PPIs by specifying CPU id, so that every PPI > > is bound to specific target CPU. But for SPIs, it always pass '0' for > > cpuid, from my understanding this means VM will set interrupt affinity > > to VCPU0 by default; in theory we also can set different cpuid for > > SPIs so that the SPIs also can be handled by other secondary VCPUs; > > this is why I think @cpuid also can be used by SPIs. > > SPIs are not hardcoded to vcpu0. This would be a gross violation of the > architecture. To convince yourself of this, just run a guest: > > root@unassigned-hostname:~# cat /proc/interrupts > CPU0 CPU1 > 2: 7315 7353 GIC-0 27 Level arch_timer > 4: 158 0 GIC-0 33 Level uart-pl011 > 42: 0 0 GIC-0 23 Level arm-pmu > 43: 0 0 pl061 3 Edge ACPI:Event > 44: 0 0 MSI 32768 Edge virtio1-config > 45: 10476 0 MSI 32769 Edge virtio1-req.0 > 46: 0 0 MSI 16384 Edge virtio0-config > 47: 3 10 MSI 16385 Edge virtio0-input.0 > [...] > > On this last line, you can see an SPI being routed to both of these > vcpus. > > I urge you to read the code further, and understand that for any other > interrupt class, the cpuid parameter is *ignored*. Yes, we pass zero in > that case. We could also pass an approximation of PI with the same > effect. Very appreciate for the elaborated example; will read the code furthermore. > The interrupt affinity is either defined by the distributor > configuration (SPIs) or the ITS configuration (LPIs). Given to the up example, I am struggling to understand how you can set the interrupt affinity for virtio device. Do you set the physical interrupt affinity to CPU0/1 in host OS and forward it to guest OS? Or set interrupt affinity in guest OS (I tried on Juno board to set irq affinity in guest OS from '/proc/irq/xxx/smp_affinity' but failed)? Or this is accomplished by user space tool (lkvm or qemu)? Sorry if I am asking a stupid question :) Thanks, Leo Yan