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[45.79.107.191]) by smtp.gmail.com with ESMTPSA id z77sm1492048pfi.155.2019.03.02.04.59.58 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 02 Mar 2019 05:00:01 -0800 (PST) Date: Sat, 2 Mar 2019 20:59:55 +0800 From: Leo Yan To: Shiwanglai Cc: "robh+dt@kernel.org" , "mark.rutland@arm.com" , "john.stultz@linaro.org" , "xuwei (O)" , "linux-arm-kernel@lists.infradead.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "coresight@lists.linaro.org" , Suzhuangluan Subject: Re: [PATCH v2] dts: arm64: add CoreSight trace support for hi3660 Message-ID: <20190302125955.GA11385@leoy-ThinkPad-X240s> References: <6496F4728C09F6479CFF21A8E67D33D568F32660@dggema525-mbx.china.huawei.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <6496F4728C09F6479CFF21A8E67D33D568F32660@dggema525-mbx.china.huawei.com> User-Agent: Mutt/1.9.4 (2018-02-28) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sat, Mar 02, 2019 at 09:45:22AM +0000, Shiwanglai wrote: [...] > > + /* Top internals */ > > + funnel@ec031000 { > > + compatible = "arm,coresight-funnel", "arm,primecell"; > > + reg = <0 0xec031000 0 0x1000>; > > + clocks = <&crg_ctrl HI3660_PCLK>; > > + clock-names = "apb_pclk"; > > + > > + out-ports { > > + port { > > + top_funnel_out: endpoint { > > + remote-endpoint = > > + <&top_etf_in>; > > + }; > > + }; > > + }; > > + > > + in-ports { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + port@0 { > > + reg = <0>; > > + top_funnel_in0: endpoint { > > + remote-endpoint = > > + <&cluster0_etf_out>; > > + }; > > + }; > > + > > + port@1 { > > + reg = <0>; > > Here should s/<0>/<1>; otherwise DTC will complain warning for mismatching between 'port@1' and 'reg = <0>'. > -- if reg set to 1, then there's no data output from cluster 1 to top. Thanks for the info, Wanglai. Now I see why write as it is. I can confirm if directly use your patch with perf with mainline kernel I can capture CoreSight trace data successfully on Hikey960 board. But since this DT binding will introduce DTC warning, I personally think we can improve for this with below method: We can create a funnel node named "funnel_combo", and we don't need to specify register address range for it; and cluster 0 and cluster 1 will output to "funnel_combo" and "funnel_combo" will output to the top funnel. Thus the DT binding will write as below. To support for a funnel without any register address range (we have support replicator like this mode), we also need to extend the driver drivers/hwtracing/coresight/coresight-funnel.c. Mathieu, Mike, Suzuki, could you help confirm this is the right direction we should move forward to? ---8<--- /* An invisible combo funnel between clusters and top funnel */ funnel_combo { compatible = "arm,coresight-funnel"; clocks = <&crg_ctrl HI3660_PCLK>; clock-names = "apb_pclk"; out-ports { port { combo_funnel_out: endpoint { remote-endpoint = <&top_funnel_in>; }; }; }; in-ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; combo_funnel_in0: endpoint { remote-endpoint = <&cluster0_etf_out>; }; }; port@1 { reg = <1>; combo_funnel_in1: endpoint { remote-endpoint = <&cluster1_etf_out>; }; }; }; }; /* Top internals */ funnel@ec031000 { compatible = "arm,coresight-funnel", "arm,primecell"; reg = <0 0xec031000 0 0x1000>; clocks = <&crg_ctrl HI3660_PCLK>; clock-names = "apb_pclk"; out-ports { port { top_funnel_out: endpoint { remote-endpoint = <&top_etf_in>; }; }; }; in-ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; top_funnel_in: endpoint { remote-endpoint = <&combo_funnel_out>; }; }; }; }; --->8--- [...] Thanks, Leo Yan