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[90.63.244.31]) by smtp.gmail.com with ESMTPSA id r15sm5756563wrt.37.2019.03.07.07.13.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 07 Mar 2019 07:13:49 -0800 (PST) From: Neil Armstrong To: khilman@baylibre.com Cc: Neil Armstrong , linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 8/9] arm64: dts: meson: g12a: Add G12A USB nodes Date: Thu, 7 Mar 2019 16:13:40 +0100 Message-Id: <20190307151342.7381-9-narmstrong@baylibre.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190307151342.7381-1-narmstrong@baylibre.com> References: <20190307151342.7381-1-narmstrong@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch adds the nodes for the USB Complex found in the Amlogic G12A SoC. It includes the : - 2 USB2 PHYs - 1 USB3 + PCIE Combo PHY - the USB Glue with it's DWC2 and DWC3 sub-nodes Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 78 +++++++++++++++++++++ 1 file changed, 78 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi index 3bcddd412aa1..991883ea023c 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi @@ -3,9 +3,13 @@ * Copyright (c) 2018 Amlogic, Inc. All rights reserved. */ +#include #include +#include +#include #include #include +#include / { compatible = "amlogic,g12a"; @@ -170,6 +174,26 @@ }; }; + usb2_phy0: phy@36000 { + compatible = "amlogic,g12a-usb2-phy"; + reg = <0x0 0x36000 0x0 0x2000>; + clocks = <&xtal>; + clock-names = "xtal"; + resets = <&reset RESET_USB_PHY20>; + reset-names = "phy"; + #phy-cells = <0>; + }; + + usb2_phy1: phy@3a000 { + compatible = "amlogic,g12a-usb2-phy"; + reg = <0x0 0x3a000 0x0 0x2000>; + clocks = <&xtal>; + clock-names = "xtal"; + resets = <&reset RESET_USB_PHY21>; + reset-names = "phy"; + #phy-cells = <0>; + }; + hiu: bus@3c000 { compatible = "simple-bus"; reg = <0x0 0x3c000 0x0 0x1400>; @@ -190,6 +214,18 @@ }; }; }; + + usb3_pcie_phy: phy@46000 { + compatible = "amlogic,g12a-usb3-pcie-phy"; + reg = <0x0 0x46000 0x0 0x2000>; + clocks = <&clkc CLKID_PCIE_PLL>; + clock-names = "ref_clk"; + resets = <&reset RESET_PCIE_PHY>; + reset-names = "phy"; + assigned-clocks = <&clkc CLKID_PCIE_PLL>; + assigned-clock-rates = <100000000>; + #phy-cells = <1>; + }; }; aobus: bus@ff800000 { @@ -353,6 +389,48 @@ status = "disabled"; }; }; + + usb: usb@ffe09000 { + status = "disabled"; + compatible = "amlogic,meson-g12a-usb-ctrl"; + reg = <0x0 0xffe09000 0x0 0xa0>; + interrupts = ; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks = <&clkc CLKID_USB>; + resets = <&reset RESET_USB>; + + dr_mode = "otg"; + + phys = <&usb2_phy0>, <&usb2_phy1>, + <&usb3_pcie_phy PHY_TYPE_USB3>; + phy-names = "usb2-phy0", "usb2-phy1", "usb3-phy0"; + + dwc2: usb@ff400000 { + compatible = "amlogic,meson-g12a-usb", "snps,dwc2"; + reg = <0x0 0xff400000 0x0 0x40000>; + interrupts = ; + clocks = <&clkc CLKID_USB1_DDR_BRIDGE>; + clock-names = "ddr"; + phys = <&usb2_phy1>; + dr_mode = "peripheral"; + g-rx-fifo-size = <192>; + g-np-tx-fifo-size = <128>; + g-tx-fifo-size = <128 128 16 16 16>; + status = "disabled"; + }; + + dwc3: usb@ff500000 { + compatible = "snps,dwc3"; + reg = <0x0 0xff500000 0x0 0x100000>; + interrupts = ; + dr_mode = "host"; + snps,dis_u2_susphy_quirk; + snps,quirk-frame-length-adjustment; + }; + }; }; timer { -- 2.20.1