From: Peter Zijlstra <peterz@infradead.org>
To: Andi Kleen <ak@linux.intel.com>
Cc: kan.liang@linux.intel.com, acme@kernel.org, mingo@redhat.com,
linux-kernel@vger.kernel.org, tglx@linutronix.de,
jolsa@kernel.org, eranian@google.com,
alexander.shishkin@linux.intel.com
Subject: Re: [PATCH 03/22] perf/x86/intel: Support adaptive PEBSv4
Date: Tue, 19 Mar 2019 17:11:31 +0100 [thread overview]
Message-ID: <20190319161131.GM5996@hirez.programming.kicks-ass.net> (raw)
In-Reply-To: <20190319160337.GW24002@tassilo.jf.intel.com>
On Tue, Mar 19, 2019 at 09:03:37AM -0700, Andi Kleen wrote:
> On Tue, Mar 19, 2019 at 03:47:48PM +0100, Peter Zijlstra wrote:
> > On Mon, Mar 18, 2019 at 02:41:25PM -0700, kan.liang@linux.intel.com wrote:
> > > From: Kan Liang <kan.liang@linux.intel.com>
> > >
> > > Adaptive PEBS is a new way to report PEBS sampling information. Instead
> > > of a fixed size record for all PEBS events it allows to configure the
> > > PEBS record to only include the information needed. Events can then opt
> > > in to use such an extended record, or stay with a basic record which
> > > only contains the IP.
> > >
> > > The major new feature is to support LBRs in PEBS record.
> > > This allows (much faster) large PEBS, while still supporting callstacks
> > > through callstack LBR.
> >
> > Does it also allow normal LBR usage? Or does it have to be callstacks?
>
> It allows normal LBR too. But I would expect callstack to be the most
> common one. As long as you set a period you can get multi-record
> PEBS with -g, which has a lot lower lower overhead than using
> PMIs.
>
> Eventually I hope we can even make multi-record PEBS
> work in frequency mode by averaging the frequency over multiple
> records.
Should be doable..
> > > hwc->config |= ARCH_PERFMON_EVENTSEL_INT;
> > > + hwc->config &= ~ICL_EVENTSEL_ADAPTIVE;
> >
> > Just curious; the way I read the SDM, we could leave this set, is that
> > correct?
>
> It needs to be cleared to get the basic record (which should be
> a common case)
But you unconditionally set the bit when you enable PEBS for the event.
So why clear it?
next prev parent reply other threads:[~2019-03-19 16:11 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-18 21:41 [PATCH 00/22] perf: Add Icelake support kan.liang
2019-03-18 21:41 ` [PATCH 01/22] perf/core: Support outputting registers from a separate array kan.liang
2019-03-19 13:00 ` Peter Zijlstra
2019-03-19 14:13 ` Peter Zijlstra
2019-03-18 21:41 ` [PATCH 02/22] perf/x86/intel: Extract memory code PEBS parser for reuse kan.liang
2019-03-19 13:14 ` Peter Zijlstra
2019-03-18 21:41 ` [PATCH 03/22] perf/x86/intel: Support adaptive PEBSv4 kan.liang
2019-03-19 14:47 ` Peter Zijlstra
2019-03-19 16:03 ` Andi Kleen
2019-03-19 16:11 ` Peter Zijlstra [this message]
2019-03-19 21:20 ` Liang, Kan
2019-03-19 21:38 ` Andi Kleen
2019-03-20 15:58 ` Peter Zijlstra
2019-03-18 21:41 ` [PATCH 04/22] perf/x86/lbr: Avoid reading the LBRs when adaptive PEBS handles them kan.liang
2019-03-18 21:41 ` [PATCH 05/22] perf/x86: Support constraint ranges kan.liang
2019-03-19 14:53 ` Peter Zijlstra
2019-03-19 15:27 ` Peter Zijlstra
2019-03-19 15:57 ` Andi Kleen
2019-03-19 16:09 ` Peter Zijlstra
2019-03-18 21:41 ` [PATCH 06/22] perf/x86/intel: Add Icelake support kan.liang
2019-03-20 0:08 ` Stephane Eranian
2019-03-20 14:20 ` Liang, Kan
2019-03-18 21:41 ` [PATCH 07/22] perf/x86/intel/cstate: " kan.liang
2019-03-18 21:41 ` [PATCH 08/22] perf/x86/intel/rapl: " kan.liang
2019-03-18 21:41 ` [PATCH 09/22] perf/x86/msr: " kan.liang
2019-03-18 21:41 ` [PATCH 10/22] perf/x86/intel/uncore: Add Intel Icelake uncore support kan.liang
2019-03-18 21:41 ` [PATCH 11/22] perf/core: Support a REMOVE transaction kan.liang
2019-03-19 15:29 ` Peter Zijlstra
2019-03-18 21:41 ` [PATCH 12/22] perf/x86/intel: Basic support for metrics counters kan.liang
2019-03-18 21:41 ` [PATCH 13/22] perf/x86/intel: Support overflows on SLOTS kan.liang
2019-03-18 21:41 ` [PATCH 14/22] perf/x86/intel: Support hardware TopDown metrics kan.liang
2019-03-18 21:41 ` [PATCH 15/22] perf/x86/intel: Set correct weight for topdown subevent counters kan.liang
2019-03-18 21:41 ` [PATCH 16/22] perf/x86/intel: Export new top down events for Icelake kan.liang
2019-03-18 21:41 ` [PATCH 17/22] perf/x86/intel: Disable sampling read slots and topdown kan.liang
2019-03-18 21:41 ` [PATCH 18/22] perf/x86/intel: Support CPUID 10.ECX to disable fixed counters kan.liang
2019-03-18 21:41 ` [PATCH 19/22] perf, tools: Add support for recording and printing XMM registers kan.liang
2019-03-18 21:41 ` [PATCH 20/22] perf, tools, stat: Support new per thread TopDown metrics kan.liang
2019-03-18 21:41 ` [PATCH 21/22] perf, tools: Add documentation for topdown metrics kan.liang
2019-03-18 21:41 ` [PATCH 22/22] perf vendor events intel: Add JSON files for Icelake kan.liang
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