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[24.22.235.96]) by smtp.gmail.com with ESMTPSA id o76sm16154476pfa.156.2019.03.21.20.29.29 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 21 Mar 2019 20:29:30 -0700 (PDT) From: Andrey Smirnov To: dri-devel@lists.freedesktop.org Cc: Andrey Smirnov , Laurent Pinchart , Archit Taneja , Andrzej Hajda , Laurent Pinchart , Tomi Valkeinen , Andrey Gusakov , Philipp Zabel , Chris Healy , Lucas Stach , linux-kernel@vger.kernel.org Subject: [PATCH v2 12/15] drm/bridge: tc358767: Introduce tc_pllupdate_pllen() Date: Thu, 21 Mar 2019 20:28:58 -0700 Message-Id: <20190322032901.12045-13-andrew.smirnov@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190322032901.12045-1-andrew.smirnov@gmail.com> References: <20190322032901.12045-1-andrew.smirnov@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org tc_wait_pll_lock() is always called as a follow-up for updating PLLUPDATE and PLLEN bit of a given PLL control register. To simplify things, merge the two operation into a single helper function tc_pllupdate_pllen() and convert the rest of the code to use it. No functional change intended. Signed-off-by: Andrey Smirnov Reviewed-by: Laurent Pinchart Cc: Archit Taneja Cc: Andrzej Hajda Cc: Laurent Pinchart Cc: Tomi Valkeinen Cc: Andrey Gusakov Cc: Philipp Zabel Cc: Chris Healy Cc: Lucas Stach Cc: dri-devel@lists.freedesktop.org Cc: linux-kernel@vger.kernel.org --- drivers/gpu/drm/bridge/tc358767.c | 32 +++++++++++++++---------------- 1 file changed, 15 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c index 976a9861e537..f66a1c4a2047 100644 --- a/drivers/gpu/drm/bridge/tc358767.c +++ b/drivers/gpu/drm/bridge/tc358767.c @@ -447,10 +447,18 @@ static u32 tc_srcctrl(struct tc_data *tc) return reg; } -static void tc_wait_pll_lock(struct tc_data *tc) +static int tc_pllupdate_pllen(struct tc_data *tc, unsigned int pllctrl) { + int ret; + + ret = regmap_write(tc->regmap, pllctrl, PLLUPDATE | PLLEN); + if (ret) + return ret; + /* Wait for PLL to lock: up to 2.09 ms, depending on refclk */ usleep_range(3000, 6000); + + return 0; } static int tc_pxl_pll_en(struct tc_data *tc, u32 refclk, u32 pixelclock) @@ -550,13 +558,7 @@ static int tc_pxl_pll_en(struct tc_data *tc, u32 refclk, u32 pixelclock) return ret; /* Force PLL parameter update and disable bypass */ - ret = regmap_write(tc->regmap, PXL_PLLCTRL, PLLUPDATE | PLLEN); - if (ret) - return ret; - - tc_wait_pll_lock(tc); - - return 0; + return tc_pllupdate_pllen(tc, PXL_PLLCTRL); } static int tc_pxl_pll_dis(struct tc_data *tc) @@ -615,7 +617,6 @@ static int tc_set_syspllparam(struct tc_data *tc) static int tc_aux_link_setup(struct tc_data *tc) { int ret; - u32 dp_phy_ctrl; u32 dp0_auxcfg1; /* Setup DP-PHY / PLL */ @@ -630,15 +631,13 @@ static int tc_aux_link_setup(struct tc_data *tc) * Initially PLLs are in bypass. Force PLL parameter update, * disable PLL bypass, enable PLL */ - ret = regmap_write(tc->regmap, DP0_PLLCTRL, PLLUPDATE | PLLEN); + ret = tc_pllupdate_pllen(tc, DP0_PLLCTRL); if (ret) goto err; - tc_wait_pll_lock(tc); - ret = regmap_write(tc->regmap, DP1_PLLCTRL, PLLUPDATE | PLLEN); + ret = tc_pllupdate_pllen(tc, DP1_PLLCTRL); if (ret) goto err; - tc_wait_pll_lock(tc); ret = tc_poll_timeout(tc, DP_PHY_CTRL, PHY_RDY, PHY_RDY, 1, 1000); if (ret == -ETIMEDOUT) { @@ -823,6 +822,7 @@ static int tc_main_link_enable(struct tc_data *tc) { struct drm_dp_aux *aux = &tc->aux; struct device *dev = tc->dev; + u32 dp_phy_ctrl; u32 value; int ret; u8 tmp[8]; @@ -858,15 +858,13 @@ static int tc_main_link_enable(struct tc_data *tc) return ret; /* PLL setup */ - ret = regmap_write(tc->regmap, DP0_PLLCTRL, PLLUPDATE | PLLEN); + ret = tc_pllupdate_pllen(tc, DP0_PLLCTRL); if (ret) return ret; - tc_wait_pll_lock(tc); - ret = regmap_write(tc->regmap, DP1_PLLCTRL, PLLUPDATE | PLLEN); + ret = tc_pllupdate_pllen(tc, DP1_PLLCTRL); if (ret) return ret; - tc_wait_pll_lock(tc); /* Reset/Enable Main Links */ dp_phy_ctrl |= DP_PHY_RST | PHY_M1_RST | PHY_M0_RST; -- 2.20.1