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From: Roger Quadros <rogerq@ti.com>
To: <kishon@ti.com>
Cc: <nsekhar@ti.com>, <vigneshr@ti.com>,
	<linux-kernel@vger.kernel.org>, Roger Quadros <rogerq@ti.com>
Subject: [PATCH 0/4] phy: ti-pipe3: Match TRM sequence & settings
Date: Fri, 22 Mar 2019 10:58:03 +0200	[thread overview]
Message-ID: <20190322085807.30216-1-rogerq@ti.com> (raw)

Hi Kishon,

We need to follow the TRM sequence and settings to ensure
that the DPLL & PHY operates correctly over the entire
temperature range.

Tested for SATA and USB. PCIe not tested.

Since this is a bug fix, please queue this for v5.1-rc. Thanks.

cheers,
-roger

Roger Quadros (4):
  phy: ti-pipe3: Introduce mode property in driver data
  phy: ti-pipe3: improve DPLL stability for SATA & USB
  phy: ti-pipe3: Fix SATA & USB PHY power up sequence
  phy: ti-pipe3: Fix PCIe power up sequence

 drivers/phy/ti/phy-ti-pipe3.c | 362 +++++++++++++++++++++++++---------
 1 file changed, 265 insertions(+), 97 deletions(-)

-- 
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Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki


             reply	other threads:[~2019-03-22  8:58 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-03-22  8:58 Roger Quadros [this message]
2019-03-22  8:58 ` [PATCH 1/4] phy: ti-pipe3: Introduce mode property in driver data Roger Quadros
2019-03-22  8:58 ` [PATCH 2/4] phy: ti-pipe3: improve DPLL stability for SATA & USB Roger Quadros
2019-03-22  8:58 ` [PATCH 3/4] phy: ti-pipe3: Fix SATA & USB PHY power up sequence Roger Quadros
2019-03-22  8:58 ` [PATCH 4/4] phy: ti-pipe3: Fix PCIe " Roger Quadros

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