From: Christoph Hellwig <hch@infradead.org>
To: Alistair Francis <alistair23@gmail.com>
Cc: Christoph Hellwig <hch@infradead.org>,
Alistair Francis <Alistair.Francis@wdc.com>,
"palmer@sifive.com" <palmer@sifive.com>,
"linux-riscv@lists.infradead.org"
<linux-riscv@lists.infradead.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH] irqchip: plic: Fix priority base offset
Date: Fri, 22 Mar 2019 06:27:48 -0700 [thread overview]
Message-ID: <20190322132748.GD19263@infradead.org> (raw)
In-Reply-To: <CAKmqyKPsoi7F_NNLKcm269=VAgdvsUV7HdF3dtkpMBzaKbHhtA@mail.gmail.com>
On Wed, Mar 20, 2019 at 05:04:58PM -0700, Alistair Francis wrote:
> > Well, it starts at 0x00, but the first one is reserved. If you think
> > that is too confusing I'd rather throw in a comment explaining this
> > fact rather than making the calculating more complicated.
>
> It doesn't mention that it starts at 0 when you look here:
> https://sifive.cdn.prismic.io/sifive%2F834354f0-08e6-423c-bf1f-0cb58ef14061_fu540-c000-v1.0.pdf
It doesn't say that. But it is completely obvious from the map,
and from how everything else works. In this case I think the
documentation is simply written in a confusing way, and we need to fix
it once we have an official riscv spec level documentation of this
hardware.
next prev parent reply other threads:[~2019-03-22 13:27 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-20 22:39 Alistair Francis
2019-03-20 23:48 ` Christoph Hellwig
2019-03-21 0:04 ` Alistair Francis
2019-03-22 13:27 ` Christoph Hellwig [this message]
2019-03-26 22:26 ` Alistair Francis
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