From: Mark Brown <broonie@kernel.org>
To: "Randolph Maaßen" <gaireg@gaireg.de>
Cc: Sowjanya Komatineni <skomatineni@nvidia.com>,
Laxman Dewangan <ldewangan@nvidia.com>,
Thierry Reding <thierry.reding@gmail.com>,
Jonathan Hunter <jonathanh@nvidia.com>,
linux-spi@vger.kernel.org, linux-tegra@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2] spi: tegra20-slink: change chip select action order
Date: Mon, 1 Apr 2019 16:17:53 +0700 [thread overview]
Message-ID: <20190401091753.GP2059@sirena.org.uk> (raw)
In-Reply-To: <20190329174411.13832-1-gaireg@gaireg.de>
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On Fri, Mar 29, 2019 at 06:44:11PM +0100, Randolph Maaßen wrote:
> To transfer via SPI the tegra20-slink driver first sets the command
> register, which contains the chip select value, and after that the
> command2 register, which contains the chip select line. This leads to a
> small spike in the chip selct 0 line between the set of the value and
> the selection of the chip select line.
Please do not submit new versions of already applied patches, please
submit incremental updates to the existing code. Modifying existing
commits creates problems for other users building on top of those
commits so it's best practice to only change pubished git commits if
absolutely essential.
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prev parent reply other threads:[~2019-04-02 4:25 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-29 17:44 Randolph Maaßen
2019-04-01 9:17 ` Mark Brown [this message]
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