From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.5 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED, USER_AGENT_MUTT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F3E19C4360F for ; Tue, 2 Apr 2019 20:40:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id CBECB2084B for ; Tue, 2 Apr 2019 20:40:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726530AbfDBUkj (ORCPT ); Tue, 2 Apr 2019 16:40:39 -0400 Received: from mga01.intel.com ([192.55.52.88]:59022 "EHLO mga01.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726193AbfDBUkj (ORCPT ); Tue, 2 Apr 2019 16:40:39 -0400 X-Amp-Result: UNKNOWN X-Amp-Original-Verdict: FILE UNKNOWN X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 02 Apr 2019 13:40:38 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,302,1549958400"; d="scan'208";a="130904603" Received: from sjchrist-coffee.jf.intel.com (HELO linux.intel.com) ([10.54.74.181]) by orsmga008.jf.intel.com with ESMTP; 02 Apr 2019 13:40:38 -0700 Date: Tue, 2 Apr 2019 13:40:38 -0700 From: Sean Christopherson To: Yang Weijiang Cc: pbonzini@redhat.com, kvm@vger.kernel.org, mst@redhat.com, rkrcmar@redhat.com, jmattson@google.com, linux-kernel@vger.kernel.org, yu-cheng.yu@intel.com, Zhang Yi Z Subject: Re: [RFC PATCH v4 2/8] KVM:CPUID: Add CET CPUID support for Guest Message-ID: <20190402204038.GM31303@linux.intel.com> References: <20190318150351.15550-1-weijiang.yang@intel.com> <20190318150351.15550-3-weijiang.yang@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20190318150351.15550-3-weijiang.yang@intel.com> User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Mar 18, 2019 at 11:03:45PM +0800, Yang Weijiang wrote: > CET SHSTK and IBT capability are reported via > CPUID.(EAX=7, ECX=0):ECX[bit 7] and EDX[bit 20] respectively. > CR4.CET[bit 23] is CET master enable bit, it controls CET feature > enabling. CET user mode and supervisor mode xsaves component size > is reported via CPUID.(EAX=0xD, ECX=1):ECX[bit 11] and ECX[bit 12] > respectively. > > Note: Although SHSTK or IBT can be enabled independently, > both of them are controlled by CR4.CET. > > Signed-off-by: Zhang Yi Z > Signed-off-by: Yang Weijiang > --- > arch/x86/include/asm/kvm_host.h | 4 +++- > arch/x86/kvm/cpuid.c | 41 ++++++++++++++++++++++----------- > arch/x86/kvm/vmx.c | 6 +++++ > arch/x86/kvm/x86.h | 4 ++++ > 4 files changed, 40 insertions(+), 15 deletions(-) > > diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h > index 55e51ff7e421..fc038bf1924a 100644 > --- a/arch/x86/include/asm/kvm_host.h > +++ b/arch/x86/include/asm/kvm_host.h > @@ -90,7 +90,8 @@ > | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR | X86_CR4_PCIDE \ > | X86_CR4_OSXSAVE | X86_CR4_SMEP | X86_CR4_FSGSBASE \ > | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_VMXE \ > - | X86_CR4_SMAP | X86_CR4_PKE | X86_CR4_UMIP)) > + | X86_CR4_SMAP | X86_CR4_PKE | X86_CR4_UMIP \ > + | X86_CR4_CET)) > > #define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR) > > @@ -1185,6 +1186,7 @@ struct kvm_x86_ops { > > int (*nested_enable_evmcs)(struct kvm_vcpu *vcpu, > uint16_t *vmcs_version); > + u64 (*vmx_supported_xss)(void); Heh, the purpose of kvm_x86_ops is to abstract things a bit, i.e. drop the "vmx" prefix. > }; > > struct kvm_arch_async_pf {