From: Mathieu Poirier <mathieu.poirier@linaro.org>
To: linux-arm-kernel@lists.infradead.org
Cc: alexander.shishkin@linux.intel.com, peterz@infradead.org,
suzuki.poulose@arm.com, mike.leach@arm.com, leo.yan@linaro.org,
coresight@lists.linaro.org, linux-kernel@vger.kernel.org
Subject: [PATCH v3 17/20] coresight: tmc-etr: Allocate and free ETR memory buffers for CPU-wide scenarios
Date: Wed, 3 Apr 2019 21:35:38 -0600 [thread overview]
Message-ID: <20190404033541.14072-18-mathieu.poirier@linaro.org> (raw)
In-Reply-To: <20190404033541.14072-1-mathieu.poirier@linaro.org>
This patch uses the PID of the process being traced to allocate and free
ETR memory buffers for CPU-wide scenarios. The implementation is tailored
to handle both N:1 and 1:1 source/sink HW topologies.
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
.../hwtracing/coresight/coresight-tmc-etr.c | 107 +++++++++++++++++-
1 file changed, 104 insertions(+), 3 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c
index 1346474ac019..61110ef41d00 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etr.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c
@@ -8,6 +8,8 @@
#include <linux/coresight.h>
#include <linux/dma-mapping.h>
#include <linux/iommu.h>
+#include <linux/idr.h>
+#include <linux/mutex.h>
#include <linux/refcount.h>
#include <linux/slab.h>
#include <linux/types.h>
@@ -26,6 +28,7 @@ struct etr_flat_buf {
/*
* etr_perf_buffer - Perf buffer used for ETR
+ * @drvdata - The ETR drvdaga this buffer has been allocated for.
* @etr_buf - Actual buffer used by the ETR
* @pid - The PID this etr_perf_buffer belongs to.
* @snaphost - Perf session mode
@@ -34,6 +37,7 @@ struct etr_flat_buf {
* @pages - Array of Pages in the ring buffer.
*/
struct etr_perf_buffer {
+ struct tmc_drvdata *drvdata;
struct etr_buf *etr_buf;
pid_t pid;
bool snapshot;
@@ -1210,6 +1214,72 @@ alloc_etr_buf(struct tmc_drvdata *drvdata, struct perf_event *event,
return etr_buf;
}
+static struct etr_buf *
+get_perf_etr_buf_cpu_wide(struct tmc_drvdata *drvdata,
+ struct perf_event *event, int nr_pages,
+ void **pages, bool snapshot)
+{
+ int ret;
+ pid_t pid = task_pid_nr(event->owner);
+ struct etr_buf *etr_buf;
+
+retry:
+ /*
+ * An etr_perf_buffer is associated with an event and holds a reference
+ * to the AUX ring buffer that was created for that event. In CPU-wide
+ * N:1 mode multiple events (one per CPU), each with its own AUX ring
+ * buffer, share a sink. As such an etr_perf_buffer is created for each
+ * event but a single etr_buf associated with the ETR is shared between
+ * them. The last event in a trace session will copy the content of the
+ * etr_buf to its AUX ring buffer. Ring buffer associated to other
+ * events are simply not used an freed as events are destoyed. We still
+ * need to allocate a ring buffer for each event since we don't know
+ * which event will be last.
+ */
+
+ /*
+ * The first thing to do here is check if an etr_buf has already been
+ * allocated for this session. If so it is shared with this event,
+ * otherwise it is created.
+ */
+ mutex_lock(&drvdata->idr_mutex);
+ etr_buf = idr_find(&drvdata->idr, pid);
+ if (etr_buf) {
+ refcount_inc(&etr_buf->refcount);
+ mutex_unlock(&drvdata->idr_mutex);
+ return etr_buf;
+ }
+
+ /* If we made it here no buffer has been allocated, do so now. */
+ mutex_unlock(&drvdata->idr_mutex);
+
+ etr_buf = alloc_etr_buf(drvdata, event, nr_pages, pages, snapshot);
+ if (IS_ERR(etr_buf))
+ return etr_buf;
+
+ refcount_set(&etr_buf->refcount, 1);
+
+ /* Now that we have a buffer, add it to the IDR. */
+ mutex_lock(&drvdata->idr_mutex);
+ ret = idr_alloc(&drvdata->idr, etr_buf, pid, pid + 1, GFP_KERNEL);
+ mutex_unlock(&drvdata->idr_mutex);
+
+ /* Another event with this session ID has allocated this buffer. */
+ if (ret == -ENOSPC) {
+ tmc_free_etr_buf(etr_buf);
+ goto retry;
+ }
+
+ /* The IDR can't allocate room for a new session, abandon ship. */
+ if (ret == -ENOMEM) {
+ tmc_free_etr_buf(etr_buf);
+ return ERR_PTR(ret);
+ }
+
+
+ return etr_buf;
+}
+
static struct etr_buf *
get_perf_etr_buf_per_thread(struct tmc_drvdata *drvdata,
struct perf_event *event, int nr_pages,
@@ -1238,7 +1308,8 @@ get_perf_etr_buf(struct tmc_drvdata *drvdata, struct perf_event *event,
return get_perf_etr_buf_per_thread(drvdata, event, nr_pages,
pages, snapshot);
- return ERR_PTR(-ENOENT);
+ return get_perf_etr_buf_cpu_wide(drvdata, event, nr_pages,
+ pages, snapshot);
}
static struct etr_perf_buffer *
@@ -1265,7 +1336,13 @@ tmc_etr_setup_perf_buf(struct tmc_drvdata *drvdata, struct perf_event *event,
return ERR_PTR(-ENOMEM);
done:
+ /*
+ * Keep a reference to the ETR this buffer has been allocated for
+ * in order to have access to the IDR in tmc_free_etr_buffer().
+ */
+ etr_perf->drvdata = drvdata;
etr_perf->etr_buf = etr_buf;
+
return etr_perf;
}
@@ -1295,9 +1372,33 @@ static void *tmc_alloc_etr_buffer(struct coresight_device *csdev,
static void tmc_free_etr_buffer(void *config)
{
struct etr_perf_buffer *etr_perf = config;
+ struct tmc_drvdata *drvdata = etr_perf->drvdata;
+ struct etr_buf *buf, *etr_buf = etr_perf->etr_buf;
+
+ if (!etr_buf)
+ goto free_etr_perf_buffer;
+
+ mutex_lock(&drvdata->idr_mutex);
+ /* If we are not the last one to use the buffer, don't touch it. */
+ if (!refcount_dec_and_test(&etr_buf->refcount)) {
+ mutex_unlock(&drvdata->idr_mutex);
+ goto free_etr_perf_buffer;
+ }
+
+ /* We are the last one, remove from the IDR and free the buffer. */
+ buf = idr_remove(&drvdata->idr, etr_perf->pid);
+ mutex_unlock(&drvdata->idr_mutex);
+
+ /*
+ * Something went very wrong if the buffer associated with this ID
+ * is not the same in the IDR. Leak to avoid use after free.
+ */
+ if (buf && WARN_ON(buf != etr_buf))
+ goto free_etr_perf_buffer;
+
+ tmc_free_etr_buf(etr_perf->etr_buf);
- if (etr_perf->etr_buf)
- tmc_free_etr_buf(etr_perf->etr_buf);
+free_etr_perf_buffer:
kfree(etr_perf);
}
--
2.17.1
next prev parent reply other threads:[~2019-04-04 3:36 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-04-04 3:35 [PATCH v3 00/20] coresight: Add support for CPU-wide trace scenarios Mathieu Poirier
2019-04-04 3:35 ` [PATCH v3 01/20] coresight: pmu: Adding ITRACE property to cs_etm PMU Mathieu Poirier
2019-04-04 8:48 ` Suzuki K Poulose
2019-04-04 3:35 ` [PATCH v3 02/20] coresight: etm4x: Add kernel configuration for CONTEXTID Mathieu Poirier
2019-04-04 8:53 ` Suzuki K Poulose
2019-04-04 3:35 ` [PATCH v3 03/20] coresight: etm4x: Skip selector pair 0 Mathieu Poirier
2019-04-04 8:50 ` Suzuki K Poulose
2019-04-04 3:35 ` [PATCH v3 04/20] coresight: etm4x: Configure tracers to emit timestamps Mathieu Poirier
2019-04-04 4:47 ` Mike Leach
2019-04-04 3:35 ` [PATCH v3 05/20] coresight: Adding return code to sink::disable() operation Mathieu Poirier
2019-04-04 3:35 ` [PATCH v3 06/20] coresight: Move reference counting inside sink drivers Mathieu Poirier
2019-04-04 3:35 ` [PATCH v3 07/20] coresight: Properly address errors in sink::disable() functions Mathieu Poirier
2019-04-04 3:35 ` [PATCH v3 08/20] coresight: Properly address concurrency in sink::update() functions Mathieu Poirier
2019-04-04 3:35 ` [PATCH v3 09/20] coresight: perf: Clean up function etm_setup_aux() Mathieu Poirier
2019-04-04 3:35 ` [PATCH v3 10/20] coresight: perf: Refactor function free_event_data() Mathieu Poirier
2019-04-04 3:35 ` [PATCH v3 11/20] coresight: Communicate perf event to sink buffer allocation functions Mathieu Poirier
2019-04-04 3:35 ` [PATCH v3 12/20] coresight: tmc-etr: Refactor function tmc_etr_setup_perf_buf() Mathieu Poirier
2019-04-04 3:35 ` [PATCH v3 13/20] coresight: tmc-etr: Create per-thread buffer allocation function Mathieu Poirier
2019-04-04 3:35 ` [PATCH v3 14/20] coresight: tmc-etr: Introduce the notion of process ID to ETR devices Mathieu Poirier
2019-04-04 3:35 ` [PATCH v3 15/20] coresight: tmc-etr: Introduce the notion of reference counting " Mathieu Poirier
2019-04-04 3:35 ` [PATCH v3 16/20] coresight: tmc-etr: Introduce the notion of IDR " Mathieu Poirier
2019-04-04 3:35 ` Mathieu Poirier [this message]
2019-04-04 3:35 ` [PATCH v3 18/20] coresight: tmc-etr: Add support for CPU-wide trace scenarios Mathieu Poirier
2019-04-04 3:35 ` [PATCH v3 19/20] coresight: tmc-etf: " Mathieu Poirier
2019-04-04 3:35 ` [PATCH v3 20/20] coresight: etb10: " Mathieu Poirier
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