From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.5 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_PASS,USER_AGENT_MUTT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4AACAC282CE for ; Fri, 5 Apr 2019 16:30:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1DDCE2146F for ; Fri, 5 Apr 2019 16:30:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731576AbfDEQag (ORCPT ); Fri, 5 Apr 2019 12:30:36 -0400 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:52608 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730554AbfDEQaf (ORCPT ); Fri, 5 Apr 2019 12:30:35 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5AB27168F; Fri, 5 Apr 2019 09:30:35 -0700 (PDT) Received: from fuggles.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A84133F68F; Fri, 5 Apr 2019 09:30:31 -0700 (PDT) Date: Fri, 5 Apr 2019 17:30:27 +0100 From: Will Deacon To: Linus Torvalds Cc: linux-arch , Linux List Kernel Mailing , "Paul E. McKenney" , Benjamin Herrenschmidt , Michael Ellerman , Arnd Bergmann , Peter Zijlstra , Andrea Parri , Palmer Dabbelt , Daniel Lustig , David Howells , Alan Stern , "Maciej W. Rozycki" , Paul Burton , Ingo Molnar , Yoshinori Sato , Rich Felker , Tony Luck , Mikulas Patocka , Akira Yokosawa , Luis Chamberlain , Nicholas Piggin Subject: Re: [PATCH v2 00/21] Remove Mysterious Macro Intended to Obscure Weird Behaviours (mmiowb()) Message-ID: <20190405163027.GA19813@fuggles.cambridge.arm.com> References: <20190405135936.7266-1-will.deacon@arm.com> <20190405160919.GA7857@fuggles.cambridge.arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.11.1+86 (6f28e57d73f2) () Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Apr 05, 2019 at 06:15:12AM -1000, Linus Torvalds wrote: > On Fri, Apr 5, 2019 at 6:09 AM Will Deacon wrote: > > > > > > Or did I miss something? I think the ia64() mb/rmb/wmb stuff only > > > works on normal memory on ia64. > > > > I was worried about RISC-V, but actually their wmb() is "fence ow,ow" > > which I think is stronger than their mmiowb() "fence o,w" implementation. > > Also with smp_store_release -> smp_load_acquire kind of ordering? Hmm, to be honest, I'm not convinced that smp_load_acquire() is ordered wrt subsequent I/O on RISC-V anyway, so in the pattern of: CPU 0: writel(1, dev); wmb(); smp_store_release(&x, 1); CPU 1: if (smp_load_acquire(&x) == 1) writel(2, dev) then I think it's actually the control dependency in CPU 1 that provides the expected ordering. That's probably quite fragile. > Again, this is not at all a NAK - I think we should do this - just > perhaps a request to add a note to the commit and make people aware of > the issue. Right, I'll do that. Will