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[24.22.235.96]) by smtp.gmail.com with ESMTPSA id 17sm49206730pfw.65.2019.04.05.10.30.19 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 05 Apr 2019 10:30:20 -0700 (PDT) From: Andrey Smirnov To: Shawn Guo Cc: Andrey Smirnov , Lucas Stach , Fabio Estevam , Fabio Estevam , Chris Healy , Leonard Crestez , "A.s. Dong" , Richard Zhu , linux-imx@nxp.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 3/5] arm64: dts: imx8mq: Combine PCIE power domains Date: Fri, 5 Apr 2019 10:30:02 -0700 Message-Id: <20190405173004.13277-4-andrew.smirnov@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190405173004.13277-1-andrew.smirnov@gmail.com> References: <20190405173004.13277-1-andrew.smirnov@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org According to NXP's FAE feedback and a comment in ATF firmware, PCIE1 and PCIE2 power domains can't really be used independently. Due to shared reset line both power domains have to be turned on at the same time. Account for that quirk by combining PCIE power domains into a single 'pgc_pcie' power domain. Signed-off-by: Andrey Smirnov Reviewed-by: Lucas Stach Reviewed-by: Fabio Estevam Cc: Shawn Guo Cc: Fabio Estevam Cc: Chris Healy Cc: Lucas Stach Cc: Leonard Crestez Cc: "A.s. Dong" Cc: Richard Zhu Cc: linux-imx@nxp.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org --- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 83d023aaa048..a85c3bef66c2 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -472,9 +472,25 @@ reg = ; }; - pgc_pcie1: power-domain@1 { + /* + * As per comment in ATF source code: + * + * PCIE1 and PCIE2 share the + * same reset signal, if we + * power down PCIE2, PCIE1 + * will be held in reset too. + * + * So instead of creating two + * separate power domains for + * PCIE1 and PCIE2 we create a + * link between both and use + * it as a shared PCIE power + * domain. + */ + pgc_pcie: power-domain@1 { #power-domain-cells = <0>; reg = ; + power-domains = <&pgc_pcie2>; }; pgc_otg1: power-domain@2 { -- 2.20.1