From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 25933C10F0E for ; Sun, 7 Apr 2019 21:34:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D461D20863 for ; Sun, 7 Apr 2019 21:34:33 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="YFksdJVJ" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726511AbfDGVec (ORCPT ); Sun, 7 Apr 2019 17:34:32 -0400 Received: from mail-pg1-f195.google.com ([209.85.215.195]:35114 "EHLO mail-pg1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726366AbfDGVec (ORCPT ); Sun, 7 Apr 2019 17:34:32 -0400 Received: by mail-pg1-f195.google.com with SMTP id g8so6120819pgf.2 for ; Sun, 07 Apr 2019 14:34:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=9pkqFjFvyFDvGw2zQrpF3FMptKmAFkz1TtHM3/eK1XQ=; b=YFksdJVJ82XArZ76OXgkuOoi56Iatx410EsvcVhUpiI7cLnWkRgszu+qLEpM6wXZyj UWuQzENcAsGLleXEJ/+g4UCoaUzP8hQSABW2d5Xw2lUmRxPNJyH2jbCbj4OKOP+9WVxZ z2voe4L5zsytn7ZzDneN9iRymQ1l0jZGAlVmlhwvxT4cgkVRErc805FNEsslwMqq/UgJ XL1/zkkD+QUqgjj7AJI72o1nbKeaB1YYUYdfbkKdXcJHbDXTs/XHj7PcmOU7VXeWEhtj istowp9bkJYEgLOW+xlE2OUItpSg+pHNEN6/Uzmh6eoHH9L7FvddAv5dGJNYTg2t7/Uo gEMg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=9pkqFjFvyFDvGw2zQrpF3FMptKmAFkz1TtHM3/eK1XQ=; b=rtrWJ4qNXqx4IZgpDLSVO3rfpkz7tJ0auAbyRRbSr7YUSX4hB7oSyWyYXcXx/E9Ij9 zJR4YcqXCj7/2pfDPJSL9T9/qaMqH3CPoRAFHnggGdnNqSN9k6BBAsVvgjP7ICoRUtnl tGpAMaJ+ShmnzgKLu3r16soGeF65As8vA53LdSi4Yx0JZ7rQProhtdzXijGjbdBcOZbz h1k5hUpClzUtXvf5Br3MM31mhvauyjsKdMVtNS7mm/9N+3GF5WBLD69ep9J51CU6dwfF I5lq1XsR623PH2mrJdm0RjJBaD4Ai7ZMG2f+j5cRO5ah4gO5of+z8Rvr6eKofIbMAjbu hrzw== X-Gm-Message-State: APjAAAUWfvEwgnmsh6447lOIcNyJAWzJvSTYBQCEoh2SsWxfgnejefUL zt2PlzC1YpF/OsnP4rY+VhPx8DIg X-Google-Smtp-Source: APXvYqxZSSXYJWWhCQA/qs0AZ8Lo40YPYb6FY9e56xJ9f7dJM2HdEqmtdDoQToNVLEIO0AmGf1AOzA== X-Received: by 2002:a63:5ec2:: with SMTP id s185mr25136912pgb.27.1554672870658; Sun, 07 Apr 2019 14:34:30 -0700 (PDT) Received: from fainelli-desktop.igp.broadcom.net ([192.19.223.250]) by smtp.gmail.com with ESMTPSA id e23sm39372233pfd.11.2019.04.07.14.34.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 07 Apr 2019 14:34:29 -0700 (PDT) From: Florian Fainelli To: linux-kernel@vger.kernel.org Cc: Florian Fainelli , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Will Deacon , Mark Rutland , Catalin Marinas , linux-arm-kernel@lists.infradead.org (moderated list:ARM PMU PROFILING AND DEBUGGING) Subject: [PATCH] perf vendor events arm64: Add Cortex-A72 events Date: Sun, 7 Apr 2019 14:34:22 -0700 Message-Id: <20190407213422.19059-1-f.fainelli@gmail.com> X-Mailer: git-send-email 2.17.1 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The Cortex-A72 supports all ARMv8 recommended events up to the RC_ST_SPEC (0x91) event, create an appropriate JSON file for mapping those events and update the mapfile.csv for matching the Cortex-A72 MIDR to that file. Signed-off-by: Florian Fainelli --- .../arm64/arm/cortex-a72/core-imp-def.json | 206 ++++++++++++++++++ tools/perf/pmu-events/arch/arm64/mapfile.csv | 1 + 2 files changed, 207 insertions(+) create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a72/core-imp-def.json diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a72/core-imp-def.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a72/core-imp-def.json new file mode 100644 index 000000000000..eb82fc8529c6 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a72/core-imp-def.json @@ -0,0 +1,206 @@ +[ + { + "ArchStdEvent": "L1D_CACHE_RD", + }, + { + "ArchStdEvent": "L1D_CACHE_WR", + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL_RD", + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL_WR", + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL_INNER", + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL_OUTER", + }, + { + "ArchStdEvent": "L1D_CACHE_WB_VICTIM", + }, + { + "ArchStdEvent": "L1D_CACHE_WB_CLEAN", + }, + { + "ArchStdEvent": "L1D_CACHE_INVAL", + }, + { + "ArchStdEvent": "L1D_TLB_REFILL_RD", + }, + { + "ArchStdEvent": "L1D_TLB_REFILL_WR", + }, + { + "ArchStdEvent": "L1D_TLB_RD", + }, + { + "ArchStdEvent": "L1D_TLB_WR", + }, + { + "ArchStdEvent": "L2D_CACHE_RD", + }, + { + "ArchStdEvent": "L2D_CACHE_WR", + }, + { + "ArchStdEvent": "L2D_CACHE_REFILL_RD", + }, + { + "ArchStdEvent": "L2D_CACHE_REFILL_WR", + }, + { + "ArchStdEvent": "L2D_CACHE_WB_VICTIM", + }, + { + "ArchStdEvent": "L2D_CACHE_WB_CLEAN", + }, + { + "ArchStdEvent": "L2D_CACHE_INVAL", + }, + { + "ArchStdEvent": "L2D_TLB_REFILL_RD", + }, + { + "ArchStdEvent": "L2D_TLB_REFILL_WR", + }, + { + "ArchStdEvent": "L2D_TLB_RD", + }, + { + "ArchStdEvent": "L2D_TLB_WR", + }, + { + "ArchStdEvent": "BUS_ACCESS_RD", + }, + { + "ArchStdEvent": "BUS_ACCESS_WR", + }, + { + "ArchStdEvent": "BUS_ACCESS_SHARED", + }, + { + "ArchStdEvent": "BUS_ACCESS_NOT_SHARED", + }, + { + "ArchStdEvent": "BUS_ACCESS_NORMAL", + }, + { + "ArchStdEvent": "BUS_ACCESS_PERIPH", + }, + { + "ArchStdEvent": "MEM_ACCESS_RD", + }, + { + "ArchStdEvent": "MEM_ACCESS_WR", + }, + { + "ArchStdEvent": "UNALIGNED_LD_SPEC", + }, + { + "ArchStdEvent": "UNALIGNED_ST_SPEC", + }, + { + "ArchStdEvent": "UNALIGNED_LDST_SPEC", + }, + { + "ArchStdEvent": "LDREX_SPEC", + }, + { + "ArchStdEvent": "STREX_PASS_SPEC", + }, + { + "ArchStdEvent": "STREX_FAIL_SPEC", + }, + { + "ArchStdEvent": "STREX_SPEC", + }, + { + "ArchStdEvent": "LD_SPEC", + }, + { + "ArchStdEvent": "ST_SPEC", + }, + { + "ArchStdEvent": "LDST_SPEC", + }, + { + "ArchStdEvent": "DP_SPEC", + }, + { + "ArchStdEvent": "ASE_SPEC", + }, + { + "ArchStdEvent": "VFP_SPEC", + }, + { + "ArchStdEvent": "PC_WRITE_SPEC", + }, + { + "ArchStdEvent": "CRYPTO_SPEC", + }, + { + "ArchStdEvent": "BR_IMMED_SPEC", + }, + { + "ArchStdEvent": "BR_RETURN_SPEC", + }, + { + "ArchStdEvent": "BR_INDIRECT_SPEC", + }, + { + "ArchStdEvent": "ISB_SPEC", + }, + { + "ArchStdEvent": "DSB_SPEC", + }, + { + "ArchStdEvent": "DMB_SPEC", + }, + { + "ArchStdEvent": "EXC_UNDEF", + }, + { + "ArchStdEvent": "EXC_SVC", + }, + { + "ArchStdEvent": "EXC_PABORT", + }, + { + "ArchStdEvent": "EXC_DABORT", + }, + { + "ArchStdEvent": "EXC_IRQ", + }, + { + "ArchStdEvent": "EXC_FIQ", + }, + { + "ArchStdEvent": "EXC_SMC", + }, + { + "ArchStdEvent": "EXC_HVC", + }, + { + "ArchStdEvent": "EXC_TRAP_PABORT", + }, + { + "ArchStdEvent": "EXC_TRAP_DABORT", + }, + { + "ArchStdEvent": "EXC_TRAP_OTHER", + }, + { + "ArchStdEvent": "EXC_TRAP_IRQ", + }, + { + "ArchStdEvent": "EXC_TRAP_FIQ", + }, + { + "ArchStdEvent": "RC_LD_SPEC", + }, + { + "ArchStdEvent": "RC_ST_SPEC", + }, +] diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv index 59cd8604b0bd..716d59248e82 100644 --- a/tools/perf/pmu-events/arch/arm64/mapfile.csv +++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv @@ -13,6 +13,7 @@ # #Family-model,Version,Filename,EventType 0x00000000410fd03[[:xdigit:]],v1,arm/cortex-a53,core +0x00000000410fd08[[:xdigit:]],v1,arm/cortex-a72,core 0x00000000420f5160,v1,cavium/thunderx2,core 0x00000000430f0af0,v1,cavium/thunderx2,core 0x00000000480fd010,v1,hisilicon/hip08,core -- 2.17.1