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[24.22.235.96]) by smtp.gmail.com with ESMTPSA id i17sm16042496pfo.103.2019.05.12.20.59.22 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 12 May 2019 20:59:23 -0700 (PDT) From: Andrey Smirnov To: Shawn Guo Cc: Andrey Smirnov , Chris Healy , Andrew Lunn , Fabio Estevam , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/2] ARM: dts: vf610-zii-dev: Add QSPI node Date: Sun, 12 May 2019 20:59:09 -0700 Message-Id: <20190513035909.30460-2-andrew.smirnov@gmail.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190513035909.30460-1-andrew.smirnov@gmail.com> References: <20190513035909.30460-1-andrew.smirnov@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Both rev C and rev B of the board come with two QSPI-NOR chips attached to the SoC. Add DT code describing all of this. Signed-off-by: Andrey Smirnov Cc: Shawn Guo Cc: Chris Healy Cc: Andrew Lunn Cc: Fabio Estevam Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org --- arch/arm/boot/dts/vf610-zii-dev.dtsi | 48 ++++++++++++++++++++++++---- 1 file changed, 42 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/vf610-zii-dev.dtsi b/arch/arm/boot/dts/vf610-zii-dev.dtsi index 5246c75e848c..f63a470f78ce 100644 --- a/arch/arm/boot/dts/vf610-zii-dev.dtsi +++ b/arch/arm/boot/dts/vf610-zii-dev.dtsi @@ -177,6 +177,36 @@ status = "okay"; }; +&qspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi0>; + status = "okay"; + + /* + * Attached MT25QL02 can go up to 90Mhz in DTR and 166 in SDR + * modes, so we limit spi-max-frequency to 90Mhz + */ + flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <90000000>; + spi-rx-bus-width = <4>; + reg = <0>; + m25p,fast-read; + }; + + flash@2 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <90000000>; + spi-rx-bus-width = <4>; + reg = <2>; + m25p,fast-read; + }; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; @@ -360,12 +390,18 @@ pinctrl_qspi0: qspi0grp { fsl,pins = < - VF610_PAD_PTD7__QSPI0_B_QSCK 0x31c3 - VF610_PAD_PTD8__QSPI0_B_CS0 0x31ff - VF610_PAD_PTD9__QSPI0_B_DATA3 0x31c3 - VF610_PAD_PTD10__QSPI0_B_DATA2 0x31c3 - VF610_PAD_PTD11__QSPI0_B_DATA1 0x31c3 - VF610_PAD_PTD12__QSPI0_B_DATA0 0x31c3 + VF610_PAD_PTD0__QSPI0_A_QSCK 0x38c2 + VF610_PAD_PTD1__QSPI0_A_CS0 0x38c2 + VF610_PAD_PTD2__QSPI0_A_DATA3 0x38c3 + VF610_PAD_PTD3__QSPI0_A_DATA2 0x38c3 + VF610_PAD_PTD4__QSPI0_A_DATA1 0x38c3 + VF610_PAD_PTD5__QSPI0_A_DATA0 0x38c3 + VF610_PAD_PTD7__QSPI0_B_QSCK 0x38c2 + VF610_PAD_PTD8__QSPI0_B_CS0 0x38c2 + VF610_PAD_PTD9__QSPI0_B_DATA3 0x38c3 + VF610_PAD_PTD10__QSPI0_B_DATA2 0x38c3 + VF610_PAD_PTD11__QSPI0_B_DATA1 0x38c3 + VF610_PAD_PTD12__QSPI0_B_DATA0 0x38c3 >; }; -- 2.21.0