From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.3 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,UNWANTED_LANGUAGE_BODY,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 33ECCC28CC2 for ; Wed, 29 May 2019 10:56:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 00A13216FD for ; Wed, 29 May 2019 10:56:59 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="om7565SC" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726820AbfE2K46 (ORCPT ); Wed, 29 May 2019 06:56:58 -0400 Received: from mail-pf1-f194.google.com ([209.85.210.194]:38426 "EHLO mail-pf1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726518AbfE2K44 (ORCPT ); Wed, 29 May 2019 06:56:56 -0400 Received: by mail-pf1-f194.google.com with SMTP id a186so692178pfa.5 for ; Wed, 29 May 2019 03:56:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=FC7VdAbFJbt5Yt2oZYTE4laLIpQms2Qf1Hk4QbxnMd4=; b=om7565SC6QMBm4TkCzcGMZybF8I9SYMUFwSnBoh3VTrqwDbf/k7JvM2DxCGWhGwU6g HpezHtofAmHaCAmFMFJxpcQQXe1KchV4Uuaxu91IurI6SKDmdePXgO1pYSsRGKOUsptu VyizZ6m/neWTtDTg7A4wnfLiGOxnLH4ogdjRU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=FC7VdAbFJbt5Yt2oZYTE4laLIpQms2Qf1Hk4QbxnMd4=; b=CzSFxloGJTOGw8akQZRDLAzT9+TFHRigC9d+92mvg/8A1GJyWqtsmw5Qidm+omPhaP wDbd+aDmrThJzJQhFeGNu9hph+c5czTAFo7fRuS21OS2zWu4E7iNuL96u533O07QNy1O JBRd0dx6kWlc5NauNI7YOBb5ivxe+mKTOPJh80IJ31xN4ZZKo8ABIpTGHV5ZMX2DdBQX n6SnHMvwtUrOrv09vWpPY1kkFuUFAmEOq4V0F2cV75tG8vAcefWFS/UNcpGa35mx3bK/ t8MslOTbnoSXMLPi0PJ3Jtzzb+gta+/g/wiTDFuuxR3kBTF55f8LXzbrXCwg5omYTu8O eHSw== X-Gm-Message-State: APjAAAWc10HrpuTzKqP/wfwy3hYta83ap988vgQVptOL0EY0wR6dPp9C rEGZQ5kyrvJkUV3RojtYUqAQuw== X-Google-Smtp-Source: APXvYqwUzv6fpT5l8WYEkz24+Q+O6xifgeyOMkKEAjaun9WXQsUx9B3IPyIta9hgd16B5f2u/V49LQ== X-Received: by 2002:a17:90a:35c1:: with SMTP id r59mr4285250pjb.49.1559127415044; Wed, 29 May 2019 03:56:55 -0700 (PDT) Received: from localhost.localdomain ([49.206.202.218]) by smtp.gmail.com with ESMTPSA id 184sm18974479pfa.48.2019.05.29.03.56.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 29 May 2019 03:56:54 -0700 (PDT) From: Jagan Teki To: Maxime Ripard , David Airlie , Daniel Vetter , Chen-Yu Tsai , dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Michael Trimarchi , devicetree@vger.kernel.org, linux-sunxi@googlegroups.com, linux-amarula@amarulasolutions.com, Sergey Suloev , Ryan Pannell , bshah@mykolab.com, Jagan Teki Subject: [PATCH v9 3/9] drm/sun4i: dsi: Add has_mod_clk quirk Date: Wed, 29 May 2019 16:26:09 +0530 Message-Id: <20190529105615.14027-4-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20190529105615.14027-1-jagan@amarulasolutions.com> References: <20190529105615.14027-1-jagan@amarulasolutions.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org As per the user manual, look like mod clock is not mandatory for all Allwinner MIPI DSI controllers, it is connected to CLK_DSI_SCLK for A31 and not available in A64. So add has_mod_clk quirk and process the clk accordingly. Tested-by: Merlijn Wajer Signed-off-by: Jagan Teki --- drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 38 ++++++++++++++++++-------- drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h | 5 ++++ 2 files changed, 32 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c index 3846ee91da52..ef878175a79b 100644 --- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c +++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -1154,6 +1155,7 @@ static int sun6i_dsi_probe(struct platform_device *pdev) dsi->dev = dev; dsi->host.ops = &sun6i_dsi_host_ops; dsi->host.dev = dev; + dsi->variant = of_device_get_match_data(dev); res = platform_get_resource(pdev, IORESOURCE_MEM, 0); base = devm_ioremap_resource(dev, res); @@ -1181,17 +1183,20 @@ static int sun6i_dsi_probe(struct platform_device *pdev) return PTR_ERR(dsi->reset); } - dsi->mod_clk = devm_clk_get(dev, "mod"); - if (IS_ERR(dsi->mod_clk)) { - dev_err(dev, "Couldn't get the DSI mod clock\n"); - return PTR_ERR(dsi->mod_clk); + if (dsi->variant->has_mod_clk) { + dsi->mod_clk = devm_clk_get(dev, "mod"); + if (IS_ERR(dsi->mod_clk)) { + dev_err(dev, "Couldn't get the DSI mod clock\n"); + return PTR_ERR(dsi->mod_clk); + } } /* * In order to operate properly, that clock seems to be always * set to 297MHz. */ - clk_set_rate_exclusive(dsi->mod_clk, 297000000); + if (dsi->variant->has_mod_clk) + clk_set_rate_exclusive(dsi->mod_clk, 297000000); dsi->dphy = devm_phy_get(dev, "dphy"); if (IS_ERR(dsi->dphy)) { @@ -1221,7 +1226,8 @@ static int sun6i_dsi_probe(struct platform_device *pdev) err_pm_disable: pm_runtime_disable(dev); err_unprotect_clk: - clk_rate_exclusive_put(dsi->mod_clk); + if (dsi->variant->has_mod_clk) + clk_rate_exclusive_put(dsi->mod_clk); return ret; } @@ -1233,7 +1239,8 @@ static int sun6i_dsi_remove(struct platform_device *pdev) component_del(&pdev->dev, &sun6i_dsi_ops); mipi_dsi_host_unregister(&dsi->host); pm_runtime_disable(dev); - clk_rate_exclusive_put(dsi->mod_clk); + if (dsi->variant->has_mod_clk) + clk_rate_exclusive_put(dsi->mod_clk); return 0; } @@ -1250,7 +1257,8 @@ static int __maybe_unused sun6i_dsi_runtime_resume(struct device *dev) } reset_control_deassert(dsi->reset); - clk_prepare_enable(dsi->mod_clk); + if (dsi->variant->has_mod_clk) + clk_prepare_enable(dsi->mod_clk); /* * Enable the DSI block. @@ -1278,7 +1286,8 @@ static int __maybe_unused sun6i_dsi_runtime_suspend(struct device *dev) { struct sun6i_dsi *dsi = dev_get_drvdata(dev); - clk_disable_unprepare(dsi->mod_clk); + if (dsi->variant->has_mod_clk) + clk_disable_unprepare(dsi->mod_clk); reset_control_assert(dsi->reset); regulator_disable(dsi->regulator); @@ -1291,9 +1300,16 @@ static const struct dev_pm_ops sun6i_dsi_pm_ops = { NULL) }; +static const struct sun6i_dsi_variant sun6i_a31_mipi_dsi = { + .has_mod_clk = true, +}; + static const struct of_device_id sun6i_dsi_of_table[] = { - { .compatible = "allwinner,sun6i-a31-mipi-dsi" }, - { } + { + .compatible = "allwinner,sun6i-a31-mipi-dsi", + .data = &sun6i_a31_mipi_dsi, + }, + { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, sun6i_dsi_of_table); diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h index c76b71259d2e..76874ff8e3ef 100644 --- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h +++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h @@ -15,6 +15,10 @@ #include +struct sun6i_dsi_variant { + bool has_mod_clk; +}; + struct sun6i_dsi { struct drm_connector connector; struct drm_encoder encoder; @@ -33,6 +37,7 @@ struct sun6i_dsi { struct mipi_dsi_device *device; struct drm_panel *panel; struct drm_bridge *bridge; + const struct sun6i_dsi_variant *variant; }; static inline struct sun6i_dsi *host_to_sun6i_dsi(struct mipi_dsi_host *host) -- 2.18.0.321.gffc6fa0e3