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[24.22.235.96]) by smtp.gmail.com with ESMTPSA id d132sm6527348pfd.61.2019.06.05.00.05.37 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 05 Jun 2019 00:05:39 -0700 (PDT) From: Andrey Smirnov To: dri-devel@lists.freedesktop.org Cc: Andrey Smirnov , Laurent Pinchart , Archit Taneja , Andrzej Hajda , Laurent Pinchart , Tomi Valkeinen , Andrey Gusakov , Philipp Zabel , Chris Healy , Cory Tusar , Lucas Stach , linux-kernel@vger.kernel.org Subject: [PATCH v3 11/15] drm/bridge: tc358767: Introduce tc_set_syspllparam() Date: Wed, 5 Jun 2019 00:05:03 -0700 Message-Id: <20190605070507.11417-12-andrew.smirnov@gmail.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190605070507.11417-1-andrew.smirnov@gmail.com> References: <20190605070507.11417-1-andrew.smirnov@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Move common code converting clock rate to an appropriate constant and configuring SYS_PLLPARAM register into a separate routine and convert the rest of the code to use it. No functional change intended. Signed-off-by: Andrey Smirnov Reviewed-by: Laurent Pinchart Cc: Archit Taneja Cc: Andrzej Hajda Cc: Laurent Pinchart Cc: Tomi Valkeinen Cc: Andrey Gusakov Cc: Philipp Zabel Cc: Chris Healy Cc: Cory Tusar Cc: Lucas Stach Cc: dri-devel@lists.freedesktop.org Cc: linux-kernel@vger.kernel.org --- drivers/gpu/drm/bridge/tc358767.c | 46 +++++++++++-------------------- 1 file changed, 16 insertions(+), 30 deletions(-) diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c index 7b84fbb72973..c58714daa0a1 100644 --- a/drivers/gpu/drm/bridge/tc358767.c +++ b/drivers/gpu/drm/bridge/tc358767.c @@ -601,35 +601,40 @@ static int tc_stream_clock_calc(struct tc_data *tc) return regmap_write(tc->regmap, DP0_VIDMNGEN1, 32768); } -static int tc_aux_link_setup(struct tc_data *tc) +static int tc_set_syspllparam(struct tc_data *tc) { unsigned long rate; - u32 dp0_auxcfg1; - u32 value; - int ret; + u32 pllparam = SYSCLK_SEL_LSCLK | LSCLK_DIV_2; rate = clk_get_rate(tc->refclk); switch (rate) { case 38400000: - value = REF_FREQ_38M4; + pllparam |= REF_FREQ_38M4; break; case 26000000: - value = REF_FREQ_26M; + pllparam |= REF_FREQ_26M; break; case 19200000: - value = REF_FREQ_19M2; + pllparam |= REF_FREQ_19M2; break; case 13000000: - value = REF_FREQ_13M; + pllparam |= REF_FREQ_13M; break; default: dev_err(tc->dev, "Invalid refclk rate: %lu Hz\n", rate); return -EINVAL; } + return regmap_write(tc->regmap, SYS_PLLPARAM, pllparam); +} + +static int tc_aux_link_setup(struct tc_data *tc) +{ + int ret; + u32 dp0_auxcfg1; + /* Setup DP-PHY / PLL */ - value |= SYSCLK_SEL_LSCLK | LSCLK_DIV_2; - ret = regmap_write(tc->regmap, SYS_PLLPARAM, value); + ret = tc_set_syspllparam(tc); if (ret) goto err; @@ -887,7 +892,6 @@ static int tc_main_link_enable(struct tc_data *tc) { struct drm_dp_aux *aux = &tc->aux; struct device *dev = tc->dev; - unsigned int rate; u32 dp_phy_ctrl; u32 value; int ret; @@ -915,25 +919,7 @@ static int tc_main_link_enable(struct tc_data *tc) if (ret) return ret; - rate = clk_get_rate(tc->refclk); - switch (rate) { - case 38400000: - value = REF_FREQ_38M4; - break; - case 26000000: - value = REF_FREQ_26M; - break; - case 19200000: - value = REF_FREQ_19M2; - break; - case 13000000: - value = REF_FREQ_13M; - break; - default: - return -EINVAL; - } - value |= SYSCLK_SEL_LSCLK | LSCLK_DIV_2; - ret = regmap_write(tc->regmap, SYS_PLLPARAM, value); + ret = tc_set_syspllparam(tc); if (ret) return ret; -- 2.21.0