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Date:   Wed, 5 Jun 2019 13:49:48 +0200
From:   Maxime Ripard <maxime.ripard@bootlin.com>
To:     megous@megous.com
Cc:     linux-sunxi@googlegroups.com, Chen-Yu Tsai <wens@csie.org>,
        Michael Turquette <mturquette@baylibre.com>,
        Stephen Boyd <sboyd@kernel.org>,
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        "open list:COMMON CLK FRAMEWORK" <linux-clk@vger.kernel.org>,
        open list <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2] clk: sunxi-ng: sun50i-h6-r: Fix incorrect W1 clock
 gate register
Message-ID: <20190605114948.a4m7g5zwdr23qgth@flea>
References: <20190604154036.23211-1-megous@megous.com>
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On Tue, Jun 04, 2019 at 05:40:36PM +0200, megous@megous.com wrote:
> From: Ondrej Jirman <megous@megous.com>
>
> The current code defines W1 clock gate to be at 0x1cc, overlaying it
> with the IR gate.
>
> Clock gate for r-apb1-w1 is at 0x1ec. This fixes issues with IR receiver
> causing interrupt floods on H6 (because interrupt flags can't be cleared,
> due to IR module's bus being disabled).
>
> Signed-off-by: Ondrej Jirman <megous@megous.com>
> Fixes: b7c7b05065aa77ae ("clk: sunxi-ng: add support for H6 PRCM CCU")

Applied, thanks

Maxime

--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

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