From: Christoph Hellwig <hch@infradead.org>
To: Palmer Dabbelt <palmer@sifive.com>
Cc: linux-riscv@lists.infradead.org,
Paul Walmsley <paul.walmsley@sifive.com>,
marco@decred.org, me@carlosedp.com, joel@sing.id.au,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH] RISC-V: Break load reservations during switch_to
Date: Thu, 6 Jun 2019 02:05:18 -0700 [thread overview]
Message-ID: <20190606090518.GB1369@infradead.org> (raw)
In-Reply-To: <20190605231735.26581-1-palmer@sifive.com>
On Wed, Jun 05, 2019 at 04:17:35PM -0700, Palmer Dabbelt wrote:
> REG_S ra, TASK_THREAD_RA_RA(a3)
> + /*
> + * The Linux ABI allows programs to depend on load reservations being
> + * broken on context switches, but the ISA doesn't require that the
> + * hardware ever breaks a load reservation. The only way to break a
> + * load reservation is with a store conditional, so we emit one here.
> + * Since nothing ever takes a load reservation on TASK_THREAD_RA_RA we
> + * know this will always fail, but just to be on the safe side this
> + * writes the same value that was unconditionally written by the
> + * previous instruction.
> + */
> +#if (TASK_THREAD_RA_RA != 0)
I don't think this check works as intended. TASK_THREAD_RA_RA is a
parameterized macro, thus the above would never evaluate to 0. The
error message also is rather odd while we're at it.
> +#if (__riscv_xlen == 64)
> + sc.d x0, ra, 0(a3)
> +#else
> + sc.w x0, ra, 0(a3)
> +#endif
I'd rather add an macro ala REG_S to asm.h and distinguish between the
xlen variants there:
#define REG_SC __REG_SEL(sc.d, sc.w)
next prev parent reply other threads:[~2019-06-06 9:05 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-05 23:17 Palmer Dabbelt
2019-06-06 8:37 ` Marco Peereboom
2019-06-06 9:05 ` Christoph Hellwig [this message]
2019-06-06 19:10 ` Palmer Dabbelt
2019-06-06 19:32 ` Andreas Schwab
2019-06-07 22:12 ` Palmer Dabbelt
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