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Date:   Sun, 9 Jun 2019 21:13:43 -0700
From:   Fenghua Yu <fenghua.yu@intel.com>
To:     Andy Lutomirski <luto@kernel.org>
Cc:     Thomas Gleixner <tglx@linutronix.de>,
        Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
        H Peter Anvin <hpa@zytor.com>,
        Ashok Raj <ashok.raj@intel.com>,
        Tony Luck <tony.luck@intel.com>,
        Ravi V Shankar <ravi.v.shankar@intel.com>,
        linux-kernel <linux-kernel@vger.kernel.org>, x86 <x86@kernel.org>
Subject: Re: [PATCH v4 2/5] x86/umwait: Initialize umwait control values
Message-ID: <20190610041343.GC162238@romley-ivt3.sc.intel.com>
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On Sat, Jun 08, 2019 at 03:52:42PM -0700, Andy Lutomirski wrote:
> On Fri, Jun 7, 2019 at 3:10 PM Fenghua Yu <fenghua.yu@intel.com> wrote:
> >
> > umwait or tpause allows processor to enter a light-weight
> > power/performance optimized state (C0.1 state) or an improved
> > power/performance optimized state (C0.2 state) for a period
> > specified by the instruction or until the system time limit or until
> > a store to the monitored address range in umwait.
> >
> > IA32_UMWAIT_CONTROL MSR register allows kernel to enable/disable C0.2
> > on the processor and set maximum time the processor can reside in
> > C0.1 or C0.2.
> >
> > By default C0.2 is enabled so the user wait instructions can enter the
> > C0.2 state to save more power with slower wakeup time.
> 
> Sounds good, but:
> 
> > +#define MSR_IA32_UMWAIT_CONTROL_C02            BIT(0)
> 
> > +static u32 umwait_control_cached = 100000;
> 
> The code seems to disagree.

The definition of bit[0] is: C0.2 is disabled when bit[0]=1. So
100000 means C0.2 is enabled (and max time is 100000).

Would it be better to change 
+#define MSR_IA32_UMWAIT_CONTROL_C02            BIT(0)
to
+#define MSR_IA32_UMWAIT_CONTROL_C02_DISABLED            BIT(0)
?

Thanks.

-Fenghua