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[2003:f1:33dd:a400:c4:c399:37fb:d289]) by smtp.googlemail.com with ESMTPSA id g5sm13900517wrp.29.2019.06.10.09.37.55 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Mon, 10 Jun 2019 09:37:55 -0700 (PDT) From: Martin Blumenstingl To: linux-amlogic@lists.infradead.org, khilman@baylibre.com Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, netdev@vger.kernel.org, linus.walleij@linaro.org, andrew@lunn.ch, Martin Blumenstingl Subject: [PATCH 1/4] arm64: dts: meson: g12a: x96-max: fix the Ethernet PHY reset line Date: Mon, 10 Jun 2019 18:37:33 +0200 Message-Id: <20190610163736.6187-2-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190610163736.6187-1-martin.blumenstingl@googlemail.com> References: <20190610163736.6187-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The Odroid-N2 schematics show that the following pins are used for the reset and interrupt lines: - GPIOZ_14 is the PHY interrupt line - GPIOZ_15 is the PHY reset line The GPIOZ_14 and GPIOZ_15 pins are special. The datasheet describes that they are "3.3V input tolerant open drain (OD) output pins". This means the GPIO controller can drive the output LOW to reset the PHY. To release the reset it can only switch the pin to input mode. The output cannot be driven HIGH for these pins. This requires configuring the reset line as GPIO_OPEN_DRAIN because otherwise the PHY will be stuck in "reset" state (because driving the pin HIGH seems to result in the same signal as driving it LOW). The reset line works together with a pull-up resistor (R143 in the Odroid-N2 schematics). The SoC can drive GPIOZ_14 LOW to assert the PHY reset. However, since the SoC can't drive the pin HIGH (to release the reset) we switch the mode to INPUT and let the pull-up resistor take care of driving the reset line HIGH. Switch to GPIOZ_15 for the PHY reset line instead of using GPIOZ_14 (which actually is the interrupt line). Move from the "snps" specific resets to the MDIO framework's reset-gpios because only the latter honors the GPIO flags. Use the GPIO flags (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN) to match with the pull-up resistor because this will: - drive the output LOW to reset the PHY (= active low) - switch the pin to INPUT mode so the pull-up will take the PHY out of reset Fixes: 51d116557b2044 ("arm64: dts: meson-g12a-x96-max: Add Gigabit Ethernet Support") Signed-off-by: Martin Blumenstingl --- arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts index 98bc56e650a0..24956edaf8e2 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts @@ -176,6 +176,10 @@ reg = <0>; max-speed = <1000>; eee-broken-1000t; + + reset-assert-us = <10000>; + reset-deassert-us = <10000>; + reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; }; }; @@ -186,9 +190,6 @@ phy-mode = "rgmii"; phy-handle = <&external_phy>; amlogic,tx-delay-ns = <2>; - snps,reset-gpio = <&gpio GPIOZ_14 0>; - snps,reset-delays-us = <0 10000 1000000>; - snps,reset-active-low; }; &pwm_ef { -- 2.22.0