From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.3 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, USER_AGENT_MUTT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BFE6BC4321A for ; Tue, 11 Jun 2019 12:52:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 99DBC20896 for ; Tue, 11 Jun 2019 12:52:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725811AbfFKMwE (ORCPT ); Tue, 11 Jun 2019 08:52:04 -0400 Received: from foss.arm.com ([217.140.110.172]:60610 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726992AbfFKMwE (ORCPT ); Tue, 11 Jun 2019 08:52:04 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C58E9344; Tue, 11 Jun 2019 05:52:03 -0700 (PDT) Received: from lakrids.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 55D8D3F557; Tue, 11 Jun 2019 05:52:02 -0700 (PDT) Date: Tue, 11 Jun 2019 13:52:00 +0100 From: Mark Rutland To: Julien Thierry Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, rostedt@goodmis.org, marc.zyngier@arm.com, yuzenghui@huawei.com, wanghaibin.wang@huawei.com, james.morse@arm.com, will.deacon@arm.com, catalin.marinas@arm.com, liwei391@huawei.com Subject: Re: [PATCH v4 3/8] arm64: irqflags: Add condition flags to inline asm clobber list Message-ID: <20190611125159.GC29008@lakrids.cambridge.arm.com> References: <1560245893-46998-1-git-send-email-julien.thierry@arm.com> <1560245893-46998-4-git-send-email-julien.thierry@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1560245893-46998-4-git-send-email-julien.thierry@arm.com> User-Agent: Mutt/1.11.1+11 (2f07cb52) (2018-12-01) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Jun 11, 2019 at 10:38:08AM +0100, Julien Thierry wrote: > Some of the inline assembly instruction use the condition flags and need > to include "cc" in the clobber list. > > Fixes: commit 4a503217ce37 ("arm64: irqflags: Use ICC_PMR_EL1 for interrupt masking") > Suggested-by: Marc Zyngier > Signed-off-by: Julien Thierry > Cc: Catalin Marinas > Cc: Will Deacon Acked-by: Mark Rutland Mark. > --- > arch/arm64/include/asm/irqflags.h | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/include/asm/irqflags.h b/arch/arm64/include/asm/irqflags.h > index 9c93152..fbe1aba 100644 > --- a/arch/arm64/include/asm/irqflags.h > +++ b/arch/arm64/include/asm/irqflags.h > @@ -92,7 +92,7 @@ static inline unsigned long arch_local_save_flags(void) > ARM64_HAS_IRQ_PRIO_MASKING) > : "=&r" (flags), "+r" (daif_bits) > : "r" ((unsigned long) GIC_PRIO_IRQOFF) > - : "memory"); > + : "cc", "memory"); > > return flags; > } > @@ -136,7 +136,7 @@ static inline int arch_irqs_disabled_flags(unsigned long flags) > ARM64_HAS_IRQ_PRIO_MASKING) > : "=&r" (res) > : "r" ((int) flags) > - : "memory"); > + : "cc", "memory"); > > return res; > } > -- > 1.9.1