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[2003:f1:33dd:a400:428d:5cff:feb9:9db8]) by smtp.googlemail.com with ESMTPSA id s7sm3445793wmc.2.2019.06.12.13.55.42 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Wed, 12 Jun 2019 13:55:44 -0700 (PDT) From: Martin Blumenstingl To: linux-amlogic@lists.infradead.org, khilman@baylibre.com Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, netdev@vger.kernel.org, linus.walleij@linaro.org, andrew@lunn.ch, robin.murphy@arm.com, Martin Blumenstingl Subject: [PATCH v2 0/4] Ethernet PHY reset GPIO updates for Amlogic SoCs Date: Wed, 12 Jun 2019 22:55:25 +0200 Message-Id: <20190612205529.19834-1-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.22.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org While trying to add the Ethernet PHY interrupt on the X96 Max I found that the current reset line definition is incorrect. Patch #1 fixes this. Since the fix requires moving from the deprecated "snps,reset-gpio" property to the generic Ethernet PHY reset bindings I decided to move all Amlogic boards over to the non-deprecated bindings. That's what patches #2 and #3 do. Finally I found that Odroid-N2 doesn't define the Ethernet PHY's reset GPIO yet. I don't have that board so I can't test whether it really works but based on the schematics it should. This series is a partial successor to "stmmac: honor the GPIO flags for the PHY reset GPIO" from [0]. I decided not to take Linus W.'s Reviewed-by from patch #4 of that series because I had to change the wording and I want to be sure that he's happy with that now. One quick note regarding patches #1 and #4: I decided to violate the "max 80 characters per line" (by 4 characters) limit because I find that the result is easier to read then it would be if I split the line. Changes since v1 at [1]: - fixed the reset deassert delay for RTL8211F PHYs - spotted by Robin Murphy (thank you). according to the public RTL8211E datasheet the correct values seem to be: 10ms assert, 30ms deassert - fixed the reset assert and deassert delays for IP101GR PHYs. There are two values given in the public datasheet, use the higher one (10ms instead of 2.5) - update the patch descriptions to quote the datasheets (the RTL8211F quotes are taken from the public RTL8211E datasheet because as far as I can tell the reset sequence is identical on both PHYs) [0] https://patchwork.kernel.org/cover/10983801/ [1] https://patchwork.kernel.org/cover/10985155/ Martin Blumenstingl (4): arm64: dts: meson: g12a: x96-max: fix the Ethernet PHY reset line ARM: dts: meson: switch to the generic Ethernet PHY reset bindings arm64: dts: meson: use the generic Ethernet PHY reset GPIO bindings arm64: dts: meson: g12b: odroid-n2: add the Ethernet PHY reset line arch/arm/boot/dts/meson8b-ec100.dts | 9 +++++---- arch/arm/boot/dts/meson8b-mxq.dts | 9 +++++---- arch/arm/boot/dts/meson8b-odroidc1.dts | 9 +++++---- arch/arm/boot/dts/meson8m2-mxiii-plus.dts | 8 ++++---- arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts | 7 ++++--- arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts | 4 ++++ arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts | 9 +++++---- .../arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts | 8 ++++---- arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts | 9 +++++---- arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts | 9 +++++---- arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi | 9 +++++---- arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi | 8 ++++---- arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts | 11 ++++++----- arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts | 10 +++++----- arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts | 8 ++++---- arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts | 11 ++++++----- arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts | 8 ++++---- 17 files changed, 80 insertions(+), 66 deletions(-) -- 2.22.0