From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.1 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_MUTT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1D308C31E51 for ; Tue, 18 Jun 2019 12:24:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E61F12082C for ; Tue, 18 Jun 2019 12:24:44 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=infradead.org header.i=@infradead.org header.b="NAEDJY2Y" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728765AbfFRMYn (ORCPT ); Tue, 18 Jun 2019 08:24:43 -0400 Received: from merlin.infradead.org ([205.233.59.134]:46458 "EHLO merlin.infradead.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726088AbfFRMYn (ORCPT ); Tue, 18 Jun 2019 08:24:43 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=merlin.20170209; h=In-Reply-To:Content-Type:MIME-Version: References:Message-ID:Subject:Cc:To:From:Date:Sender:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id: List-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=tD8Ldis1b1ybeeBuDIwXZsiRf2P3qbbvUlnCoUXwyuY=; b=NAEDJY2YdVxbiTrefTEuYU5Ti H/iWv7twG2VncqxpEZ4HA9OiOOSv8QEjwievCiXzhW/NSGfcW/vzV52+aDKkIiNusXXiAF+DNWkTY tIi9K4wjN9c191xRkQv3VFdN9ZmA1NyXfKlEBMakvFL+zpjrLT8AxUtW/cKyrNUAVWXkDYkj8Claj J7003OnUSqDZwVB6YyRMLERu8/3iIubOn9bCpKNZgaKCCctS982Ivx6+yk77k/TduV8XJ4Xav6ySs ghrnWuHcHMe+jBR9qyUGaC8JqHrlvmUN/4AHGMfBs7YIWfs+NWFNLPr3hVX+X7g+DOZXmExLzZOl7 qOovV3u0w==; Received: from j217100.upc-j.chello.nl ([24.132.217.100] helo=hirez.programming.kicks-ass.net) by merlin.infradead.org with esmtpsa (Exim 4.92 #3 (Red Hat Linux)) id 1hdDA7-0007Go-O0; Tue, 18 Jun 2019 12:24:32 +0000 Received: by hirez.programming.kicks-ass.net (Postfix, from userid 1000) id 3ABFA2076F70F; Tue, 18 Jun 2019 14:24:30 +0200 (CEST) Date: Tue, 18 Jun 2019 14:24:30 +0200 From: Peter Zijlstra To: Jann Horn Cc: Kees Cook , Thomas Gleixner , Linus Torvalds , the arch/x86 maintainers , Dave Hansen , kernel list , Kernel Hardening Subject: Re: [PATCH v3 3/3] x86/asm: Pin sensitive CR0 bits Message-ID: <20190618122430.GF3419@hirez.programming.kicks-ass.net> References: <20190618045503.39105-1-keescook@chromium.org> <20190618045503.39105-4-keescook@chromium.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Jun 18, 2019 at 11:38:02AM +0200, Jann Horn wrote: > On Tue, Jun 18, 2019 at 6:55 AM Kees Cook wrote: > > With sensitive CR4 bits pinned now, it's possible that the WP bit for > > CR0 might become a target as well. Following the same reasoning for > > the CR4 pinning, this pins CR0's WP bit (but this can be done with a > > static value). > > > > Suggested-by: Peter Zijlstra > > Signed-off-by: Kees Cook > > --- > > arch/x86/include/asm/special_insns.h | 15 ++++++++++++++- > > 1 file changed, 14 insertions(+), 1 deletion(-) > > > > diff --git a/arch/x86/include/asm/special_insns.h b/arch/x86/include/asm/special_insns.h > > index c8c8143ab27b..b2e84d113f2a 100644 > > --- a/arch/x86/include/asm/special_insns.h > > +++ b/arch/x86/include/asm/special_insns.h > > @@ -31,7 +31,20 @@ static inline unsigned long native_read_cr0(void) > > > > static inline void native_write_cr0(unsigned long val) > > { > > So, assuming a legitimate call to native_write_cr0(), we come in here... > > > - asm volatile("mov %0,%%cr0": : "r" (val), "m" (__force_order)); > > + unsigned long bits_missing = 0; ^^^ > > + > > +set_register: > > + asm volatile("mov %0,%%cr0": "+r" (val), "+m" (__force_order)); > > ... here we've updated CR0... > > > + if (static_branch_likely(&cr_pinning)) { > > ... this branch is taken, since cr_pinning is set to true after boot... > > > + if (unlikely((val & X86_CR0_WP) != X86_CR0_WP)) { > > ... this branch isn't taken, because a legitimate update preserves the WP bit... > > > + bits_missing = X86_CR0_WP; ^^^ > > + val |= bits_missing; > > + goto set_register; > > + } > > + /* Warn after we've set the missing bits. */ > > + WARN_ONCE(bits_missing, "CR0 WP bit went missing!?\n"); > > ... and we reach this WARN_ONCE()? Am I missing something, or does > every legitimate CR0 write after early boot now trigger a warning? bits_missing will be 0 and WARN will not be issued. > > + } > > }