From: Tao Xu <tao3.xu@intel.com>
To: pbonzini@redhat.com, rkrcmar@redhat.com, tglx@linutronix.de,
mingo@redhat.com, bp@alien8.de, hpa@zytor.com
Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org,
xiaoyao.li@linux.intel.com, tao3.xu@intel.com
Subject: [PATCH] KVM: vmx: Fix the broken usage of vmx_xsaves_supported
Date: Thu, 20 Jun 2019 13:03:01 +0800 [thread overview]
Message-ID: <20190620050301.1149-1-tao3.xu@intel.com> (raw)
The helper vmx_xsaves_supported() returns the bit value of
SECONDARY_EXEC_XSAVES in vmcs_config.cpu_based_2nd_exec_ctrl, which
remains unchanged true if vmcs supports 1-setting of this bit after
setup_vmcs_config(). It should check the guest's cpuid not this
unchanged value when get/set msr.
Besides, vmx_compute_secondary_exec_control() adjusts
SECONDARY_EXEC_XSAVES bit based on guest cpuid's X86_FEATURE_XSAVE
and X86_FEATURE_XSAVES, it should use updated value to decide whether
set XSS_EXIT_BITMAP.
Co-developed-by: Xiaoyao Li <xiaoyao.li@linux.intel.com>
Signed-off-by: Xiaoyao Li <xiaoyao.li@linux.intel.com>
Signed-off-by: Tao Xu <tao3.xu@intel.com>
---
arch/x86/kvm/vmx/vmx.c | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c
index b93e36ddee5e..935cf72439a9 100644
--- a/arch/x86/kvm/vmx/vmx.c
+++ b/arch/x86/kvm/vmx/vmx.c
@@ -1721,7 +1721,8 @@ static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
return vmx_get_vmx_msr(&vmx->nested.msrs, msr_info->index,
&msr_info->data);
case MSR_IA32_XSS:
- if (!vmx_xsaves_supported())
+ if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) ||
+ !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
return 1;
msr_info->data = vcpu->arch.ia32_xss;
break;
@@ -1935,7 +1936,8 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
return 1;
return vmx_set_vmx_msr(vcpu, msr_index, data);
case MSR_IA32_XSS:
- if (!vmx_xsaves_supported())
+ if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) ||
+ !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
return 1;
/*
* The only supported bit as of Skylake is bit 8, but
@@ -4094,7 +4096,7 @@ static void vmx_vcpu_setup(struct vcpu_vmx *vmx)
set_cr4_guest_host_mask(vmx);
- if (vmx_xsaves_supported())
+ if (vmx->secondary_exec_control & SECONDARY_EXEC_XSAVES)
vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
if (enable_pml) {
--
2.20.1
next reply other threads:[~2019-06-20 5:05 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-20 5:03 Tao Xu [this message]
2019-06-20 6:40 ` Wanpeng Li
2019-06-20 6:46 ` Xiaoyao Li
2019-06-20 8:17 ` Paolo Bonzini
2019-06-20 8:27 ` Wanpeng Li
2019-06-20 8:36 ` Paolo Bonzini
2019-06-20 8:55 ` Xiaoyao Li
2019-06-20 8:59 ` Paolo Bonzini
2019-06-20 9:02 ` Wanpeng Li
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