From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 411CDC48BD7 for ; Thu, 27 Jun 2019 08:01:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1CFAE20828 for ; Thu, 27 Jun 2019 08:01:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726437AbfF0IB0 (ORCPT ); Thu, 27 Jun 2019 04:01:26 -0400 Received: from mailgw02.mediatek.com ([1.203.163.81]:38084 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726101AbfF0IBZ (ORCPT ); Thu, 27 Jun 2019 04:01:25 -0400 X-UUID: a61b840fda2c490888e41684eee737f0-20190627 X-UUID: a61b840fda2c490888e41684eee737f0-20190627 Received: from mtkcas36.mediatek.inc [(172.27.4.253)] by mailgw02.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLS) with ESMTP id 1028844314; Thu, 27 Jun 2019 16:01:20 +0800 Received: from MTKCAS36.mediatek.inc (172.27.4.186) by MTKMBS33N1.mediatek.inc (172.27.4.75) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 27 Jun 2019 16:01:19 +0800 Received: from mszsdclx1018.gcn.mediatek.inc (172.27.4.253) by MTKCAS36.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Thu, 27 Jun 2019 16:01:17 +0800 From: Jitao Shi To: Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , , David Airlie , Matthias Brugger CC: Jitao Shi , Thierry Reding , Ajay Kumar , Inki Dae , Rahul Sharma , Sean Paul , Vincent Palatin , Andy Yan , Philipp Zabel , Russell King , , , , , , , Sascha Hauer , , , , , , Subject: [v5 0/7] Support dsi for mt8183 Date: Thu, 27 Jun 2019 16:01:08 +0800 Message-ID: <20190627080116.40264-1-jitao.shi@mediatek.com> X-Mailer: git-send-email 2.21.0 MIME-Version: 1.0 Content-Transfer-Encoding: 7BIT Content-Type: text/plain; charset=US-ASCII X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Change since v4: - move mipi_dsi_host_unregiter() to .remove() - fine tune add frame size control coding style - change the data type of data_rate as u32, and add DIV_ROUND_UP_ULL - use div_u64 when 8000000000ULL / dsi->data_rate. Changes since v3 - add one more 'tab' for bitwise define. - add Tested-by: Ryan Case and Reviewed-by: CK Hu . - remove compare da_hs_zero to da_hs_prepare. Changes since v2: - change the video timing calc method - fine the dsi and mipitx init sequence - fine tune commit msg Changes since v1: - separate frame size and reg commit control independent patches. - fix some return values in probe - remove DSI_CMDW0 in "CMDQ reg address of mt8173 is different with mt2701" Jitao Shi (7): drm/mediatek: move mipi_dsi_host_register to probe drm/mediatek: fixes CMDQ reg address of mt8173 is different with mt2701 drm/mediatek: add dsi reg commit disable control drm/mediatek: add frame size control drm/mediatek: add mt8183 dsi driver support drm/mediatek: change the dsi phytiming calculate method drm: mediatek: adjust dsi and mipi_tx probe sequence drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 +- drivers/gpu/drm/mediatek/mtk_dsi.c | 223 ++++++++++++++++++------- 2 files changed, 160 insertions(+), 65 deletions(-) -- 2.21.0