From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.7 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, UNPARSEABLE_RELAY,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C9EE4C48BD6 for ; Thu, 27 Jun 2019 08:01:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A8D0E2083B for ; Thu, 27 Jun 2019 08:01:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726651AbfF0IBq (ORCPT ); Thu, 27 Jun 2019 04:01:46 -0400 Received: from Mailgw01.mediatek.com ([1.203.163.78]:5635 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726544AbfF0IBl (ORCPT ); Thu, 27 Jun 2019 04:01:41 -0400 X-UUID: af4a2c27b60c4198b5025a5939c6f097-20190627 X-UUID: af4a2c27b60c4198b5025a5939c6f097-20190627 Received: from mtkcas35.mediatek.inc [(172.27.4.253)] by mailgw01.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLS) with ESMTP id 1262622998; Thu, 27 Jun 2019 16:01:27 +0800 Received: from MTKCAS36.mediatek.inc (172.27.4.186) by MTKMBS33DR.mediatek.inc (172.27.6.106) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 27 Jun 2019 16:01:25 +0800 Received: from mszsdclx1018.gcn.mediatek.inc (172.27.4.253) by MTKCAS36.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Thu, 27 Jun 2019 16:01:23 +0800 From: Jitao Shi To: Rob Herring , Pawel Moll , "Mark Rutland" , Ian Campbell , , David Airlie , "Matthias Brugger" CC: Jitao Shi , Thierry Reding , Ajay Kumar , Inki Dae , "Rahul Sharma" , Sean Paul , "Vincent Palatin" , Andy Yan , "Philipp Zabel" , Russell King , , , , , , , "Sascha Hauer" , , , , , , Subject: [v5 4/7] drm/mediatek: add frame size control Date: Thu, 27 Jun 2019 16:01:12 +0800 Message-ID: <20190627080116.40264-5-jitao.shi@mediatek.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190627080116.40264-1-jitao.shi@mediatek.com> References: <20190627080116.40264-1-jitao.shi@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7BIT Content-Type: text/plain; charset=US-ASCII X-TM-AS-Product-Ver: SMEX-12.5.0.1684-8.5.1010-24720.003 X-TM-AS-Result: No-7.797800-8.000000-10 X-TMASE-MatchedRID: 4fIxLVRlVoz935chln091FZ85UImhNta+eBf9ovw8I2RoQLwUmtov7BZ szSz1qei2XHJ0L4jOITTDbyTDLiYnZxBJWVIsdLqA9lly13c/gE5B3KUNlRt51VkJxysad/IJTn jWSezJPZBXFYsxXKTlvssoJBke0RlqZWpk+GKRVNIUlKkz3wfmX0tCKdnhB589yM15V5aWpj6C0 ePs7A07RQEL0GGu6SDsXWDONKz/s5QaPnzkRZpYjy4hCRTklRkE6fTC+T7uQ4= X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--7.797800-8.000000 X-TMASE-Version: SMEX-12.5.0.1684-8.5.1010-24720.003 X-TM-SNTS-SMTP: C8B5EEBD7AA18A239CFB080C5B9AB92E1996F13A41DB17C5AA1328425E81A0FC2000:8 X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Our new DSI chip has frame size control. So add the driver data to control for different chips. Signed-off-by: Jitao Shi Reviewed-by: CK Hu --- drivers/gpu/drm/mediatek/mtk_dsi.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c index 6b6550926db6..45e331055842 100644 --- a/drivers/gpu/drm/mediatek/mtk_dsi.c +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c @@ -78,6 +78,7 @@ #define DSI_VBP_NL 0x24 #define DSI_VFP_NL 0x28 #define DSI_VACT_NL 0x2C +#define DSI_SIZE_CON 0x38 #define DSI_HSA_WC 0x50 #define DSI_HBP_WC 0x54 #define DSI_HFP_WC 0x58 @@ -162,6 +163,7 @@ struct phy; struct mtk_dsi_driver_data { const u32 reg_cmdq_off; bool has_shadow_ctl; + bool has_size_ctl; }; struct mtk_dsi { @@ -430,6 +432,10 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi) writel(vm->vfront_porch, dsi->regs + DSI_VFP_NL); writel(vm->vactive, dsi->regs + DSI_VACT_NL); + if (dsi->driver_data->has_size_ctl) + writel(vm->vactive << 16 | vm->hactive, + dsi->regs + DSI_SIZE_CON); + horizontal_sync_active_byte = (vm->hsync_len * dsi_tmp_buf_bpp - 10); if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) -- 2.21.0