Re: Perf framework : Cluster based counter support

[Mark Rutland <mark.rutland@arm.com>]

On Mon, Jul 01, 2019 at 09:09:33PM +0530, Mukesh Ojha wrote:
> 
> On 6/28/2019 10:29 PM, Mark Rutland wrote:
> > On Fri, Jun 28, 2019 at 10:23:10PM +0530, Mukesh Ojha wrote:
> > > Hi All,
> > Hi Mukesh,
> > 
> > > Is it looks considerable to add cluster based event support to add in
> > > current perf event framework and later in userspace perf to support
> > > such events ?
> > Could you elaborate on what you mean by "cluster based event"?
> > 
> > I assume you mean something like events for a cluster-affine shared
> > resource like some level of cache?
> > 
> > If so, there's a standard pattern for supporting such system/uncore
> > PMUs, see drivers/perf/qcom_l2_pmu.c and friends for examples.
> 
> Thanks Mark for pointing it out.
> Also What is stopping us in adding cluster based event e.g L2 cache hit/miss
> or some other type raw events  in core framework ?

That depends on how the event is exposed.

If it's exposed via the architectural PMU, then it's already accessible
as a raw (cpu-affine) event, regardless of whether that makes sense.

If it's a separate PMU (as I suspect is the case), then it simply has to
be a separate PMU driver.

Thanks,
Mark.