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Mon, 15 Jul 2019 12:44:40 +0000 (GMT) From: Lukasz Luba To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org Cc: mturquette@baylibre.com, sboyd@kernel.org, b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, mark.rutland@arm.com, robh+dt@kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, a.hajda@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, Lukasz Luba Subject: [PATCH v1 09/50] clk: samsung: add IDs to FSYS clocks in Exynos5x Date: Mon, 15 Jul 2019 14:43:36 +0200 Message-Id: <20190715124417.4787-10-l.luba@partner.samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190715124417.4787-1-l.luba@partner.samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0VSa0hTYRju2zln52y0OG5RH2Vag6CLza7w2dUo4SAEQdCPIuqYJ43csp2m WZEr0aWYmoGKXSVTmVY6zVsqpsuZw9SFWopdVLp5LRU5ZdZOZ9a/530u7/Py8VGYupZYQp00 nOWMBjZCK1fi5U1C27oAk9+R9S5hI+p59JJAJVmPCdQ9+YlAd+3uMXVgCENtbcUkar0yTKIe szeyDXQR6FvyWwK9qr4lR1ltdTL00N5HogfdHTLU0RKEei8XyFF8rZ1EjcMWAs12leCBGqbo ThFgxl7Hk4zNmihnSnNjmWejNTImpcwKmAmbz37ykHJ7KBdxMooz+u88pgx3lOaByF+KcyXN WcAMnFQSUFCQ3gzTUgUiCSgpNV0AoLW+ApOGSQBb3lR5hgkAn8eNYnMR4eFLXBLyASyd6JT9 i4z1tbsVipLTOlhpPSMGFtK5ANqFENGD0W9ksGawihAFDR0MXSk2XMQ4vRIOtnwBYlZF74JV iQelMl9YWFz/t1jhpoWMdrm4B9IuEl5/+k4umfbCTOGm5zoN/OooIyXsDZ03knEJ89B8LQdI +CIcSL3t8WyDjY4OQuzF6NXwcbW/RO+GCYV1pEhDegF8PeIl0pgbppdnYhKtglcT1JJ7FSxL bpdJeBHML8rwLGdg4bsGz+ukAziVYyPSgG/2/7J7AFjBYs7E68M4fpOBi9bxrJ43GcJ0x0/r bcD9qZyzjqlKUDcT0gBoCmjnqwJD1x5RE2wUH6NvAJDCtAtVO6bclCqUjTnPGU8fNZoiOL4B LKVw7WLVhXnvD6vpMPYsd4rjIjnjnCqjFEvM4Jiv+lZlZ58lJ+jSAiL1W78rVhnHOpdPf/g+ 4vSKCnV+UnYHz1T8yHSkNPv7jT75Xbb1oy/Kyu41Tb+ydBQ4ogci+4XP5p+KLec3jLOznV1D sSt0+87t6U+4v+lAnqEYb+0dmbWMf2+6E6eZPjH5YqjVhNV/WKTxm/FRZQRcNC/T4nw4u2EN ZuTZPwkbD49QAwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprPIsWRmVeSWpSXmKPExsVy+t/xe7oWpTqxBi//WFvcWneO1WLjjPWs Fte/PGe1mH8EyO1//JrZ4vz5DewWZ5vesFvcapCx2PT4GqvFx557rBaXd81hs5hxfh+Txdoj d9ktll6/yGRx8ZSrxe3GFWwWrXuPsFscftPOavHv2kYWB2GPNfPWMHq8v9HK7rFpVSebx+Yl 9R4H3+1h8ujbsorR4/MmuQD2KD2bovzSklSFjPziElulaEMLIz1DSws9IxNLPUNj81grI1Ml fTublNSczLLUIn27BL2M45uXMRb85azYeGIGYwPjaY4uRk4OCQETiZ9rz7F0MXJxCAksZZTY vnUyG0RCTGLSvu3sELawxJ9rXWwQRZ8YJRZ9uQeU4OBgE9CT2LGqEKRGRGAFo8TkE94gNcwC r5kkjhx9xwqSEBbwkrjUt4kFxGYRUJV4cuolI0gvr4C9xM7OMIj58hKrNxxgBrE5gcI/p10A u0FIwE5i8dGfTBMY+RYwMqxiFEktLc5Nzy020itOzC0uzUvXS87P3cQIjJxtx35u2cHY9S74 EKMAB6MSD69DinasEGtiWXFl7iFGCQ5mJRFe269AId6UxMqq1KL8+KLSnNTiQ4ymQDdNZJYS Tc4HRnVeSbyhqaG5haWhubG5sZmFkjhvh8DBGCGB9MSS1OzU1ILUIpg+Jg5OqQbGSS9vXn+5 7n9Ckgz7LPlXR18tFriWwvBy8rOvn7s3vCnPilJO0Ejg7txyK9cniaHRoOnD3Jt/Z/WrG1Vz tT1V3vtu00nup2UCz6f57xLbu50p7u1n9UDDVeHrp62uMsud3JV22pl1+/Sa6X/5KlinfHsm FsAUe9Xhm4Z2+pJf/7lMd86cvNv2qxJLcUaioRZzUXEiAGEcT5KyAgAA X-CMS-MailID: 20190715124441eucas1p12e1f58587318219a5a2c695faa200b17 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-RootMTR: 20190715124441eucas1p12e1f58587318219a5a2c695faa200b17 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190715124441eucas1p12e1f58587318219a5a2c695faa200b17 References: <20190715124417.4787-1-l.luba@partner.samsung.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add IDs to MUXes of ACLK200_FSYS, ACLK_FSYS2, PCLK200_FSYS to manage them from DT. Signed-off-by: Lukasz Luba --- drivers/clk/samsung/clk-exynos5420.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index 5f251279b4c8..6164d0ca75e0 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -622,9 +622,12 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = { MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1), MUX(0, "mout_aclk200", mout_group1_p, SRC_TOP0, 8, 2), - MUX(0, "mout_aclk200_fsys2", mout_group1_p, SRC_TOP0, 12, 2), - MUX(0, "mout_pclk200_fsys", mout_group1_p, SRC_TOP0, 24, 2), - MUX(0, "mout_aclk200_fsys", mout_group1_p, SRC_TOP0, 28, 2), + MUX(CLK_MOUT_ACLK200_FSYS2, "mout_aclk200_fsys2", mout_group1_p, + SRC_TOP0, 12, 2), + MUX(CLK_MOUT_PCLK200_FSYS, "mout_pclk200_fsys", mout_group1_p, + SRC_TOP0, 24, 2), + MUX(CLK_MOUT_ACLK200_FSYS, "mout_aclk200_fsys", mout_group1_p, + SRC_TOP0, 28, 2), MUX(0, "mout_aclk66", mout_group1_p, SRC_TOP1, 8, 2), MUX(0, "mout_aclk166", mout_group1_p, SRC_TOP1, 24, 2), -- 2.17.1