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Wed, 17 Jul 2019 08:48:11 +0000 From: To: , CC: , , , , , , , , Subject: [PATCH 3/5] mtd: spi-nor: add Global Block Unlock support Thread-Topic: [PATCH 3/5] mtd: spi-nor: add Global Block Unlock support Thread-Index: AQHVPHxdqQl/GMdi9ECDdSKG+lyMoQ== Date: Wed, 17 Jul 2019 08:48:11 +0000 Message-ID: <20190717084745.19322-4-tudor.ambarus@microchip.com> References: <20190717084745.19322-1-tudor.ambarus@microchip.com> In-Reply-To: <20190717084745.19322-1-tudor.ambarus@microchip.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: VI1P195CA0085.EURP195.PROD.OUTLOOK.COM (2603:10a6:802:59::38) To BN6PR11MB1842.namprd11.prod.outlook.com (2603:10b6:404:101::18) x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.9.5 x-originating-ip: [94.177.32.154] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 31001b2b-fce1-46e0-3107-08d70a937f8a x-microsoft-antispam: BCL:0;PCL:0;RULEID:(2390118)(7020095)(4652040)(8989299)(5600148)(711020)(4605104)(1401327)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(2017052603328)(7193020);SRVR:BN6SPR00MB254; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 31001b2b-fce1-46e0-3107-08d70a937f8a X-MS-Exchange-CrossTenant-originalarrivaltime: 17 Jul 2019 08:48:11.4326 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3f4057f3-b418-4d4e-ba84-d55b4e897d88 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: tudor.ambarus@microchip.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6SPR00MB254 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Tudor Ambarus To avoid inadvertent writes during power-up, some flashes are write-protected by default after a power-on reset cycle. A Global Block-Protection Unlock command offers a single command cycle that unlocks the entire memory array. This is identical with what other nor flashes are doing by clearing the block protection bits from the status register: disable the write protection after a power-on reset cycle. We can't determine this purely by manufacturer type and it's not autodetectable by anything like SFDP, so make a new flag for it: UNLOCK_GLOBAL_BLOCK. Note that the Global Block Unlock command has different names depending on the manufacturer, but always the same command value: 0x98. Macronix's MX25U12835F names it Gang Block Unlock, Winbound's W25Q128FV names it Global Block Unlock and Microchip's SST26VF064B names it Global Block Protection Unlock. Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/spi-nor.c | 21 ++++++++++++++++++++- include/linux/mtd/spi-nor.h | 1 + 2 files changed, 21 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index e9e441f91b68..767e2e6eb1b8 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -250,7 +250,7 @@ struct flash_info { u16 page_size; u16 addr_width; =20 - u16 flags; + u32 flags; #define SECT_4K BIT(0) /* SPINOR_OP_BE_4K works uniformly */ #define SPI_NOR_NO_ERASE BIT(1) /* No erase command needed */ #define SST_WRITE BIT(2) /* use SST byte programming */ @@ -279,6 +279,7 @@ struct flash_info { #define SPI_NOR_SKIP_SFDP BIT(13) /* Skip parsing of SFDP tables */ #define USE_CLSR BIT(14) /* use CLSR command */ #define SPI_NOR_OCTAL_READ BIT(15) /* Flash supports Octal Read */ +#define UNLOCK_GLOBAL_BLOCK BIT(16) /* Unlock global block protection */ =20 /* Part specific fixup hooks. */ const struct spi_nor_fixups *fixups; @@ -1725,6 +1726,20 @@ static int spi_nor_spansion_clear_sr_bp(struct spi_n= or *nor) return spi_nor_clear_sr_bp(nor); } =20 +static int spi_nor_unlock_global_block_protection(struct spi_nor *nor) +{ + int ret; + + write_enable(nor); + + ret =3D nor->write_reg(nor, SPINOR_OP_ULBPR, NULL, 0); + if (ret < 0) { + dev_err(nor->dev, "error %d on ULBPR\n", ret); + return ret; + } + return spi_nor_wait_till_ready(nor); +} + /* Used when the "_ext_id" is two bytes at most */ #define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \ .id =3D { \ @@ -4053,6 +4068,10 @@ static int spi_nor_init(struct spi_nor *nor) spi_nor_spansion_clear_sr_bp; } =20 + if (nor->info->flags & UNLOCK_GLOBAL_BLOCK) + nor->disable_write_protection =3D + spi_nor_unlock_global_block_protection; + if (nor->disable_write_protection) { err =3D nor->disable_write_protection(nor); if (err) { diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index 6c3273760700..84d279fd287e 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -65,6 +65,7 @@ #define SPINOR_OP_CLFSR 0x50 /* Clear flag status register */ #define SPINOR_OP_RDEAR 0xc8 /* Read Extended Address Register */ #define SPINOR_OP_WREAR 0xc5 /* Write Extended Address Register */ +#define SPINOR_OP_ULBPR 0x98 /* Global Block Unlock Protection */ =20 /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */ #define SPINOR_OP_READ_4B 0x13 /* Read data bytes (low frequency) */ --=20 2.9.5