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Wed, 17 Jul 2019 08:48:16 +0000 From: To: , CC: , , , , , , , , Subject: [PATCH 5/5] mtd: spi-nor: add Kconfig option to disable write protection at power-up Thread-Topic: [PATCH 5/5] mtd: spi-nor: add Kconfig option to disable write protection at power-up Thread-Index: AQHVPHxf57xp/vrlsEWVvsFB8NifHg== Date: Wed, 17 Jul 2019 08:48:16 +0000 Message-ID: <20190717084745.19322-6-tudor.ambarus@microchip.com> References: <20190717084745.19322-1-tudor.ambarus@microchip.com> In-Reply-To: <20190717084745.19322-1-tudor.ambarus@microchip.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: VI1P195CA0085.EURP195.PROD.OUTLOOK.COM (2603:10a6:802:59::38) To BN6PR11MB1842.namprd11.prod.outlook.com (2603:10b6:404:101::18) x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.9.5 x-originating-ip: [94.177.32.154] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 3ba4e511-15fb-4a3a-7210-08d70a938254 x-microsoft-antispam: BCL:0;PCL:0;RULEID:(2390118)(7020095)(4652040)(8989299)(5600148)(711020)(4605104)(1401327)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(2017052603328)(7193020);SRVR:BN6SPR00MB254; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 3ba4e511-15fb-4a3a-7210-08d70a938254 X-MS-Exchange-CrossTenant-originalarrivaltime: 17 Jul 2019 08:48:16.1006 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3f4057f3-b418-4d4e-ba84-d55b4e897d88 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: tudor.ambarus@microchip.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6SPR00MB254 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Tudor Ambarus Some spi-nor flashes come write protected by default after a power-on sequence to avoid destructing commands (erase, write) during power-up. Backward compatibility imposes to disable the write protection at power-up by default. Add a Kconfig option to let the user benefit of the power-up write protection. Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/Kconfig | 8 ++++++++ drivers/mtd/spi-nor/spi-nor.c | 2 ++ 2 files changed, 10 insertions(+) diff --git a/drivers/mtd/spi-nor/Kconfig b/drivers/mtd/spi-nor/Kconfig index 6de83277ce8b..b550e10657f1 100644 --- a/drivers/mtd/spi-nor/Kconfig +++ b/drivers/mtd/spi-nor/Kconfig @@ -22,6 +22,14 @@ config MTD_SPI_NOR_USE_4K_SECTORS Please note that some tools/drivers/filesystems may not work with 4096 B erase size (e.g. UBIFS requires 15 KiB as a minimum). =20 +config MTD_SPI_NOR_DISABLE_POWER_UP_WRITE_PROTECTION + bool "Disable write protection during power-up" + default y + help + Some spi-nor flashes are write protected by default after a power-on + reset cycle, in order to avoid inadvertend writes during power-up. + Disable the write protection during power-up. + config SPI_ASPEED_SMC tristate "Aspeed flash controllers in SPI mode" depends on ARCH_ASPEED || COMPILE_TEST diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index ffb53740031c..e5627fa6b1cd 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -4049,6 +4049,7 @@ static int spi_nor_init(struct spi_nor *nor) { int err; =20 +#ifdef CONFIG_MTD_SPI_NOR_DISABLE_POWER_UP_WRITE_PROTECTION /* * Atmel, SST, Intel/Numonyx, and others serial NOR tend to power up * with the software protection bits set. @@ -4082,6 +4083,7 @@ static int spi_nor_init(struct spi_nor *nor) return err; } } +#endif =20 if (nor->quad_enable) { err =3D nor->quad_enable(nor); --=20 2.9.5