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From: Peter Zijlstra <peterz@infradead.org>
To: "Liang, Kan" <kan.liang@linux.intel.com>
Cc: Yunying Sun <yunying.sun@intel.com>,
	mingo@redhat.com, acme@kernel.org,
	alexander.shishkin@linux.intel.com, jolsa@redhat.com,
	namhyung@kernel.org, tglx@linutronix.de, bp@alien8.de,
	hpa@zytor.com, ak@linux.intel.com, x86@kernel.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH RESEND] perf/x86/intel: Bit 13 is valid for Icelake MSR_OFFCORE_RSP_x register
Date: Thu, 25 Jul 2019 09:50:31 +0200	[thread overview]
Message-ID: <20190725075031.GG31381@hirez.programming.kicks-ass.net> (raw)
In-Reply-To: <1022fe65-0f9a-52d3-2765-25aa2a326848@linux.intel.com>

On Wed, Jul 24, 2019 at 09:11:01AM -0400, Liang, Kan wrote:
> 
> 
> On 7/24/2019 4:29 AM, Yunying Sun wrote:
> >  From Intel SDM, bit 13 of Icelake MSR_OFFCORE_RSP_x register is valid for
> > counting hardware generated prefetches of L3 cache. But current bitmasks
> > in driver takes bit 13 as invalid. Here to fix it.
> > 
> > Before:
> > $ perf stat -e cpu/event=0xb7,umask=0x1,config1=0x1bfff/u sleep 3
> >   Performance counter stats for 'sleep 3':
> >     <not supported>      cpu/event=0xb7,umask=0x1,config1=0x1bfff/u
> > 
> > After:
> > $ perf stat -e cpu/event=0xb7,umask=0x1,config1=0x1bfff/u sleep 3
> >   Performance counter stats for 'sleep 3':
> >               9,293      cpu/event=0xb7,umask=0x1,config1=0x1bfff/u
> > 
> > Signed-off-by: Yunying Sun <yunying.sun@intel.com>
> 
> Thanks Yunying.
> 
> Reviewed-by: Kan Liang <kan.liang@linux.intel.com>

Thanks!

  reply	other threads:[~2019-07-25  7:50 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <20190724073911.12177-1-yunying.sun@intel.com>
2019-07-24  8:29 ` Yunying Sun
2019-07-24 13:11   ` Liang, Kan
2019-07-25  7:50     ` Peter Zijlstra [this message]
2019-07-25 16:06   ` [tip:perf/urgent] perf/x86/intel: Fix invalid Bit 13 " tip-bot for Yunying Sun

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