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[71.184.117.43]) by smtp.gmail.com with ESMTPSA id x46sm45986742qtx.96.2019.08.02.17.34.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 02 Aug 2019 17:34:23 -0700 (PDT) From: Qian Cai To: will@kernel.org, catalin.marinas@arm.com Cc: rrichter@cavium.com, robin.murphy@arm.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Qian Cai Subject: [PATCH v2] arm64/prefetch: fix a -Wtype-limits warning Date: Fri, 2 Aug 2019 20:33:58 -0400 Message-Id: <20190803003358.992-1-cai@lca.pw> X-Mailer: git-send-email 2.20.1 (Apple Git-117) MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The commit d5370f754875 ("arm64: prefetch: add alternative pattern for CPUs without a prefetcher") introduced MIDR_IS_CPU_MODEL_RANGE() to be used in has_no_hw_prefetch() with rv_min=0 which generates a compilation warning from GCC, In file included from ./arch/arm64/include/asm/cache.h:8, from ./include/linux/cache.h:6, from ./include/linux/printk.h:9, from ./include/linux/kernel.h:15, from ./include/linux/cpumask.h:10, from arch/arm64/kernel/cpufeature.c:11: arch/arm64/kernel/cpufeature.c: In function 'has_no_hw_prefetch': ./arch/arm64/include/asm/cputype.h:59:26: warning: comparison of unsigned expression >= 0 is always true [-Wtype-limits] _model == (model) && rv >= (rv_min) && rv <= (rv_max); \ ^~ arch/arm64/kernel/cpufeature.c:889:9: note: in expansion of macro 'MIDR_IS_CPU_MODEL_RANGE' return MIDR_IS_CPU_MODEL_RANGE(midr, MIDR_THUNDERX, ^~~~~~~~~~~~~~~~~~~~~~~ Fix it by making "rv" a "s32". Signed-off-by: Qian Cai --- v2: Use "s32" for "rv", so "variant 0/revision 0" can be covered. arch/arm64/include/asm/cputype.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index e7d46631cc42..d52fe8651c2d 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -54,7 +54,7 @@ #define MIDR_IS_CPU_MODEL_RANGE(midr, model, rv_min, rv_max) \ ({ \ u32 _model = (midr) & MIDR_CPU_MODEL_MASK; \ - u32 rv = (midr) & (MIDR_REVISION_MASK | MIDR_VARIANT_MASK); \ + s32 rv = (midr) & (MIDR_REVISION_MASK | MIDR_VARIANT_MASK); \ \ _model == (model) && rv >= (rv_min) && rv <= (rv_max); \ }) -- 2.20.1 (Apple Git-117)