From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 972DAC433FF for ; Tue, 6 Aug 2019 14:35:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 6B4DD2089E for ; Tue, 6 Aug 2019 14:35:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732955AbfHFOfD (ORCPT ); Tue, 6 Aug 2019 10:35:03 -0400 Received: from foss.arm.com ([217.140.110.172]:34232 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728756AbfHFOfC (ORCPT ); Tue, 6 Aug 2019 10:35:02 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C162B344; Tue, 6 Aug 2019 07:35:01 -0700 (PDT) Received: from lakrids.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id BD5F23F706; Tue, 6 Aug 2019 07:34:59 -0700 (PDT) Date: Tue, 6 Aug 2019 15:34:57 +0100 From: Mark Rutland To: Rob Clark Cc: Christoph Hellwig , Rob Clark , dri-devel , Catalin Marinas , Will Deacon , Maarten Lankhorst , Maxime Ripard , Sean Paul , David Airlie , Daniel Vetter , Allison Randal , Greg Kroah-Hartman , Thomas Gleixner , linux-arm-kernel@lists.infradead.org, LKML Subject: Re: [PATCH 1/2] drm: add cache support for arm64 Message-ID: <20190806143457.GF475@lakrids.cambridge.arm.com> References: <20190805211451.20176-1-robdclark@gmail.com> <20190806084821.GA17129@lst.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.11.1+11 (2f07cb52) (2018-12-01) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Aug 06, 2019 at 07:11:41AM -0700, Rob Clark wrote: > On Tue, Aug 6, 2019 at 1:48 AM Christoph Hellwig wrote: > > > > This goes in the wrong direction. drm_cflush_* are a bad API we need to > > get rid of, not add use of it. The reason for that is two-fold: > > > > a) it doesn't address how cache maintaince actually works in most > > platforms. When talking about a cache we three fundamental operations: > > > > 1) write back - this writes the content of the cache back to the > > backing memory > > 2) invalidate - this remove the content of the cache > > 3) write back + invalidate - do both of the above > > Agreed that drm_cflush_* isn't a great API. In this particular case > (IIUC), I need wb+inv so that there aren't dirty cache lines that drop > out to memory later, and so that I don't get a cache hit on > uncached/wc mmap'ing. Is there a cacheable alias lying around (e.g. the linear map), or are these addresses only mapped uncached/wc? If there's a cacheable alias, performing an invalidate isn't sufficient, since a CPU can allocate a new (clean) entry at any point in time (e.g. as a result of prefetching or arbitrary speculation). Thanks, Mark.