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Tue, 6 Aug 2019 17:45:55 +0000 Authentication-Results: spf=none (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; lists.freedesktop.org; dkim=none (message not signed) header.d=none;lists.freedesktop.org; dmarc=permerror action=none header.from=amd.com; Received-SPF: None (protection.outlook.com: amd.com does not designate permitted sender hosts) Received: from SATLEXCHOV01.amd.com (165.204.84.17) by BY2NAM03FT014.mail.protection.outlook.com (10.152.84.239) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.2136.14 via Frontend Transport; Tue, 6 Aug 2019 17:45:54 +0000 Received: from hwentlanhp.amd.com (10.180.168.240) by SATLEXCHOV01.amd.com (10.181.40.71) with Microsoft SMTP Server id 14.3.389.1; Tue, 6 Aug 2019 12:45:53 -0500 From: Harry Wentland To: CC: , , , , , , , , , , , , "Harry Wentland" Subject: [PATCH] drm/amd/display: Add number of slices per line to DSC parameter validation Date: Tue, 6 Aug 2019 13:45:49 -0400 Message-ID: <20190806174549.7856-1-harry.wentland@amd.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:165.204.84.17;IPV:NLI;CTRY:US;EFV:NLI;SFV:NSPM;SFS:(10009020)(4636009)(136003)(346002)(39860400002)(396003)(376002)(2980300002)(428003)(199004)(189003)(2906002)(76176011)(44832011)(68736007)(70206006)(50226002)(8936002)(70586007)(8676002)(316002)(1076003)(81166006)(81156014)(14444005)(2870700001)(53416004)(53936002)(51416003)(476003)(36756003)(126002)(47776003)(426003)(7696005)(6916009)(486006)(2616005)(11346002)(336012)(4326008)(86362001)(356004)(478600001)(54906003)(48376002)(305945005)(6666004)(2351001)(5660300002)(50466002)(26005)(186003)(446003);DIR:OUT;SFP:1101;SCL:1;SRVR:DM5PR12MB1530;H:SATLEXCHOV01.amd.com;FPR:;SPF:None;LANG:en;PTR:InfoDomainNonexistent;A:1;MX:1; X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 67ea6083-b8ab-4f03-5408-08d71a95ee50 X-Microsoft-Antispam: BCL:0;PCL:0;RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600148)(711020)(4605104)(1401327)(2017052603328);SRVR:DM5PR12MB1530; X-MS-TrafficTypeDiagnostic: DM5PR12MB1530: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2887; X-Forefront-PRVS: 0121F24F22 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam-Message-Info: uPKfIagK7X91CwB0caabnoEYD7hDSl28l/UgFOW0g0CLFcGlxNp7RY99A77wie4wvGCPi2dx4jYD0eh+rZ2Rf1ENN1Xhv1bavpXCXuknuTMScRVO/64o+145I7sfBmazUIlfKNtYUfotHAlTpz0w/gZortPsDDcCN6FSoRFUZXQpB89unrhfMlN/XdC3WlU5IltMFp5CB7XD4OCnDXqrXiu2fxF48g3kFdW/TLBgpprZmoUiaYJBRI+9GAAXnLEKDS+InsnYlJXTza4KvacIVT5joZ7GKSipfjh2UzwlsEgXA6NyWACuhjIr678j/NBNadoJui7HW4orySyTkIWVY++8ViQU8ZqevbO+69vWcDwPf5CPjpRSQQ6sFA2h28Lz7xcgAAgisfLlKnv9fdVhAvWiKI2YydHTqpwY3iWaDv0= X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Aug 2019 17:45:54.5424 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 67ea6083-b8ab-4f03-5408-08d71a95ee50 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXCHOV01.amd.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB1530 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Nikola Cornij [why] Number of slices per line was mistakenly left out Cc: Hariprasad Kelam Signed-off-by: Nikola Cornij Signed-off-by: Harry Wentland Reviewed-by: Harry Wentland --- Thanks, Hariprasad, for your patch. The second condition should actually check for num_slices_h. Harry drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c index e870caa8d4fa..adb69c038efb 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c @@ -302,7 +302,7 @@ static bool dsc_prepare_config(struct display_stream_compressor *dsc, const stru dsc_cfg->dc_dsc_cfg.linebuf_depth == 0))); ASSERT(96 <= dsc_cfg->dc_dsc_cfg.bits_per_pixel && dsc_cfg->dc_dsc_cfg.bits_per_pixel <= 0x3ff); // 6.0 <= bits_per_pixel <= 63.9375 - if (!dsc_cfg->dc_dsc_cfg.num_slices_v || !dsc_cfg->dc_dsc_cfg.num_slices_v || + if (!dsc_cfg->dc_dsc_cfg.num_slices_v || !dsc_cfg->dc_dsc_cfg.num_slices_h || !(dsc_cfg->dc_dsc_cfg.version_minor == 1 || dsc_cfg->dc_dsc_cfg.version_minor == 2) || !dsc_cfg->pic_width || !dsc_cfg->pic_height || !((dsc_cfg->dc_dsc_cfg.version_minor == 1 && // v1.1 line buffer depth range: -- 2.22.0