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[216.228.112.22]) by smtp.gmail.com with ESMTPSA id n5sm94563063pfn.38.2019.08.06.18.17.03 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 06 Aug 2019 18:17:03 -0700 (PDT) Date: Tue, 6 Aug 2019 18:17:59 -0700 From: Nicolin Chen To: Daniel Baluta Cc: broonie@kernel.org, l.stach@pengutronix.de, mihai.serban@gmail.com, alsa-devel@alsa-project.org, timur@kernel.org, shengjiu.wang@nxp.com, angus@akkea.ca, tiwai@suse.com, linux-imx@nxp.com, kernel@pengutronix.de, festevam@gmail.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, robh@kernel.org Subject: Re: [PATCH v3 2/5] ASoC: fsl_sai: Update Tx/Rx channel enable mask Message-ID: <20190807011758.GE8938@Asurada-Nvidia.nvidia.com> References: <20190806151214.6783-1-daniel.baluta@nxp.com> <20190806151214.6783-3-daniel.baluta@nxp.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20190806151214.6783-3-daniel.baluta@nxp.com> User-Agent: Mutt/1.9.4 (2018-02-28) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Aug 06, 2019 at 06:12:11PM +0300, Daniel Baluta wrote: > Tx channel enable (TCE) / Rx channel enable (RCE) bits > enable corresponding data channel for Tx/Rx operation. > > Because SAI supports up the 8 channels TCE/RCE occupy > up the 8 bits inside TCR3/RCR3 registers we need to extend > the mask to reflect this. > > Signed-off-by: Daniel Baluta Acked-by: Nicolin Chen Thanks > --- > sound/soc/fsl/fsl_sai.c | 6 ++++-- > sound/soc/fsl/fsl_sai.h | 1 + > 2 files changed, 5 insertions(+), 2 deletions(-) > > diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c > index 17b0aff4ee8b..637b1d12a575 100644 > --- a/sound/soc/fsl/fsl_sai.c > +++ b/sound/soc/fsl/fsl_sai.c > @@ -599,7 +599,8 @@ static int fsl_sai_startup(struct snd_pcm_substream *substream, > bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; > int ret; > > - regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx), FSL_SAI_CR3_TRCE, > + regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx), > + FSL_SAI_CR3_TRCE_MASK, > FSL_SAI_CR3_TRCE); > > ret = snd_pcm_hw_constraint_list(substream->runtime, 0, > @@ -614,7 +615,8 @@ static void fsl_sai_shutdown(struct snd_pcm_substream *substream, > struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); > bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; > > - regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx), FSL_SAI_CR3_TRCE, 0); > + regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx), > + FSL_SAI_CR3_TRCE_MASK, 0); > } > > static const struct snd_soc_dai_ops fsl_sai_pcm_dai_ops = { > diff --git a/sound/soc/fsl/fsl_sai.h b/sound/soc/fsl/fsl_sai.h > index 4bb478041d67..20c5b9b1e8bc 100644 > --- a/sound/soc/fsl/fsl_sai.h > +++ b/sound/soc/fsl/fsl_sai.h > @@ -110,6 +110,7 @@ > > /* SAI Transmit and Receive Configuration 3 Register */ > #define FSL_SAI_CR3_TRCE BIT(16) > +#define FSL_SAI_CR3_TRCE_MASK GENMASK(23, 16) > #define FSL_SAI_CR3_WDFL(x) (x) > #define FSL_SAI_CR3_WDFL_MASK 0x1f > > -- > 2.17.1 >